Chipworks concluded in an analysis of the 32 nm Apple A6 SoC that the six-transistor SRAM cell area was ~0.15 µm2. It estimates the same cell shrunk to the 28 nm process of the A7 would measure ~0.12 µm2. Thus it concludes the A7 sports ~1 Mbyte L2 cache and ~256 Kbyte L1 cache based on conservative 40-50 percent utilization to allow for the row and column circuitry.
Looking at the layout, Apple appears to have used 1 DDR channel to feed the CPU and another channel for GPU data. The large SRAM above the GPU appears to be the embedded cache for graphics memory, which is similar to approach used by Intel's IRIS Pro and XBOX One
To store finger print data? You need to use NVM, not SRAM or you have to keep feeding power to the chip, which is not possible
Also for the CPU highlighted by chipworks, it appears that the complex includes 2 memory controllers from layout, so the actual area for the CPU complex (excluding the memory controller) is likely smaller than 17% or ~17 sq mm
It makes more sense to me this large on-chip RAM is L-3 Cache for DRAM controller directly next to it. If I am Apple, I will never store direct finger print data in anywhere. Because wherever you store, people will figure out. A good choice is to apply special imaging hashing function to it and only store hashing value. Not sure this technology exist today.
I doubt google will jump in at this level any time soon. they've typically partnered with a hardware vendor for this kind of stuff, like microsoft. I do know they have custom hardware made for their datacenters though.
Who knows with google, they don't tend to follow a narrow path forward, so they might decide to experiment with SoC development of their own.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments