Digital Core Design (DCD) provides synthesizable IP cores for use in ASIC, ASSP, and SoC designs. These IP cores, which are available in both Verilog and HDL, come equipped with documentation, testbenches, debug tools, and so forth.
DCD specializes in taking popular microprocessors, microcontrollers, and peripheral devices, and re-engineering them to have new architectures. Although these new implementations are faster and consume less power, they are always 100 percent software compatible with their predecessors.
DCD's latest offering -- the D2692 -- is a dual universal asynchronous receiver/transmitter (DUART) IP core.
Example deployment of the D2692 IP core in an interface chip.
While maintaining compatibility with the well-known SC26C92, SCC2692, and SCN2681 DUARTs, the D2692 offers additional features, including deeper FIFOs, a watchdog timer for each receiver, support for extended baud rates, and programmable transmitter and receiver interrupts.
Click here for more information on DCD's D2692 dual UART IP core.