SAN JOSE, Calif. -- Taiwan Semiconductor Manufacturing Co. is making steady progress on its next two nodes, bringing advances in performance and low power. The bad news is it's widely expected the latest nodes add less transistor density and more cost than in the past.
TSMC has taped out several 20nm chips and expects to let customers start designing 16nm FinFET chips before the end of the year. By the end of 2014 it expects it will have taped out 25 20nm designs and be far along in work on 30 16nm chips.
Company execs gave a frank and detailed rundown of their progress, especially on the 16nm node at a Silicon Valley event here. TSMC is seen as a bellwether of the chip sector and electronics generally because it is one of the world's largest and most advanced makers of semiconductors. It puts out a whopping 1.3 million eight-inch equivalent wafers each month, some of them now down to 20nm geometries.
Both the 20 and 16nm nodes represent key turning points. The 20nm node is the first to use double patterning, requiring more masks and more runs under an immersion lithography machine. It's expected future nodes at 10nm and beyond could require triple or even quadruple patterning, raising costs again.
The 16nm node represents TSMC's first use of FinFETs, a.k.a. vertical transistors. Indeed, this node basically just adds FinFETs to the existing 20nm process, thus it provides almost no gain in packing in more transistors per area of die, although it does offer benefits in lower power or higher performance.
TSMC execs did not mention the added costs and the reduced density in talks here, and they were not available for interviews afterwards. In past events the execs remained in the hall, answering a few questions for reporters and others, but this time they left the hall directly after speaking.
Nevertheless, TSMC execs read out testimonials about its 20nm process from a handful of key customers. Oracle said it successfully taped out its M7 server processor in TSMC's 20nm node. Xilinx said it used the node for a PLD, and Altera said it is developing its latest serdes in the node. Smartphone chip giant Qualcomm said it is developing both 16 and 20nm design flows with TSMC.
TSMC's long-time chairman Morris Chang (above), 82, did not make the trip to San Jose for this event although he spoke to a crowd of several hundred engineers via a pre-recorded video. Chang's absence rekindled discussion among attendees about the succession plan at the company which has a deep bench of seasoned executives but none with the breadth of experience or clout as the man they refer to as "chairman."
"We see more opportunities, but the window to capture them is getting smaller and smaller, [requiring] heavier investment and greater complexity [so there's a] need to leverage all our expertise," Chang said in his video. "We need each other to be competitive and to win," he told the audience of partners and customers.
The following pages provide details about TSMCs progress at 20 and 16nm. They also provide a look at its ongoing work in 3D stacking technologies seen as an alternative way to gain performance and power benefits at a time when traditional techniques are becoming more complex and costly.