Breaking News
News & Analysis

TSMC Shows Path to 16nm, Beyond

Gains Come as Costs, Complexity Rise
10/2/2013 07:05 AM EDT
NO RATINGS
10 saves
Page 1 / 11 Next >
Page 1 / 4   >   >>
User Rank
Author
Re: 20nm costs
10/8/2013 12:26:05 PM
NO RATINGS
The whole idea behind FDSOI and Multi-Gate is to create a fully depleted channel in order to minimize off-state leakage.

Simply put a gate only controls a finite thickness.

For FDSOI you have one gate on top of the channel with a buried oxide underneath the channel. The silicon device layer thickness (the thickness of the film under the gate) must be 1/3 the gate length or the gate can't control the channel and achieve a fully depleted device. This is the major scaling challenge for FDSOI, it is very hard to make SOI device layers that thin.

For a FinFet you have a thin fin with two gates, one on each side "squeezing" the channel and the fin width (thickness) can be ½ the gate length and still achieve a fully depleted channel.

For a TriGate you have three gates squeezing the cahnnel from both sides of the fin and the top and the fin width (thickness) can be the same as the gate length and still achieve a fully depleted device.

Basically the more gates you have controlling the channel the thicker it can be and still be fully depleted in the off state.

There are even solutions being explored for the long term with gates on all four sides for even better control.

Please note that in each case the thickness can be smaller but not larger than the specified amount and achieve fully depleted operation.

User Rank
Author
Re: 20nm costs
10/8/2013 5:15:30 AM
NO RATINGS
Thanks for clarifying the meaning of gate length.  I still don't understand:  "For finFETs with 2 gates the fin width must be 1/2 the gate length. For TriGate the fin width is 1x the gate length making manufacturing easier."  Could you describe further?

User Rank
Author
Re: 20nm costs
10/7/2013 10:37:11 AM
NO RATINGS
By gate length I mean the gate length not gate width following the standard definition. Gate length is the HKMG gate length between the source and drain along the fin.

User Rank
Author
Re: 20nm costs
10/7/2013 4:52:39 AM
NO RATINGS
Hi,

Thanks for commenting on EUV and finFet.

>> "For fully depleted operation SOI silicon thickness has to be 1/3 the gate length and that is really hard to do as gate lengths scale down. For finFETs with 2 gates the fin width must be 1/2 the gate length. For TriGate the fin width is 1x the gate length making manufacturing easier."

Could you elaborate in detail the relationship among gate length, fin width, and trigate / dual-gate?   By "gate length", do you mean transistor width?  Isn't "gate length" also known as channel length?   Transistor width is a function of fin pitch, fin height, fin width, and whether the fin is tri- or dual- gate.  Isn't it?

In figures of IvyBridge Tri-gate 22nm process reported by Chipworks: fin_width(bottom)~=15nm, fin_height~=34nm, and gate length 23.7~24.6nm.  Fin_width(top) seems to be about of 1/2 of bottom.

User Rank
Author
Re: higher EUV NA
10/7/2013 1:48:33 AM
NO RATINGS
This has been  a very helpful discussion as I prep for an interview with an EUV expert today at IMEC.

User Rank
Author
Re: higher EUV NA
10/6/2013 11:38:09 PM
NO RATINGS
Ideally, the EUV wavelength would be continued with higher NA but this means larger angles, and the multilayer must be modified from its current status. It could impact the reflectivity and therefore the throughput. So there was also a proposal to increase the mask demagnification from 4X to 6X at least. That's another big change.

User Rank
Author
Re: dose doubling
10/6/2013 11:30:59 PM
NO RATINGS
Dose doubling comes from feature halving area each successive node but the number of photons cannot be halved, because that would increase the shot noise. The photon number should at least stay the same, but since the feature population is increasing as well, even 6 standard deviations allowed for this noise within a population of a billion may not be enough.

User Rank
Author
Re: TSMC finFET doping
10/6/2013 11:09:22 PM
NO RATINGS
I haven't seen anything specific but TSMC tends to follow Intel's technology path. I would expect the fin Vt to be set by implant and in situ doped raised eSiGe and eSiC Source/Drains. For what it is worth I expect EUV system performance NA, Flare, et . To improve over time and there to be multiple single pattern nodes. An older ASML roadmap I saw included going to a ~6.8nm wavelength around 2018 but I am told by Litho friend that there are lot of issues with that wavelength. Also I am told by my Litho expert friends that the statement earlier in this thread about dose doubling with each node is not correct.

User Rank
Author
Re: TSMC finFET doping
10/6/2013 1:45:41 AM
NO RATINGS
@currentsci: Can anyone answer the doping/HKMG questions?

At the event, TSMC didn't go into such detail in the keynotes and the break out sessions were all from partners.

User Rank
Author
TSMC finFET doping
10/4/2013 5:52:16 PM
NO RATINGS
1 saves
In all these preliminary design releases, has TSMC said anything specific on the methods used to dope the bulk finFETs, including the source/drain contants and extensnions and, most interesting, the junction isolation doping in the fin base regions?  Another key item will be the methods for workfunction tuning of the HKMG stacks.  So, do we wait for Dec and the IEDM talks & discusisons or is anything known already?

Page 1 / 4   >   >>

3/30/2017
7:08:11 PM