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TSMC Shows Path to 16nm, Beyond

Gains Come as Costs, Complexity Rise
10/2/2013 07:05 AM EDT
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rick merritt
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20nm costs
rick merritt   10/2/2013 10:13:05 AM
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How much higher aree costs at 20nm where double patterning kicks in? Enquiring minds want to know!

R_Colin_Johnson
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Re: 20nm costs
R_Colin_Johnson   10/2/2013 1:23:40 PM
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Very comprehensive report on progress at TSMC. Thanks. And your question about costs at 20nm node are very pertinent--especially now that Intel claims to already be at the 14nm node and selling its overcapacity as foundry services to Altera and otehrs!

 

ScottenJ
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Re: 20nm costs
ScottenJ   10/2/2013 3:22:48 PM
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20nm is about 24% more expensive per unit area and with 1.9x more die gives a 35% cost reduction. The problem is at 16nm where the 1.05x more die than 20nm will not offest the increased cost per unit area and the cost per die will go up.

krisi
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Re: 20nm costs
krisi   10/2/2013 4:02:26 PM
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why 1.05x between 30nm and 16nm???

ScottenJ
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Re: 20nm costs
ScottenJ   10/2/2013 4:59:22 PM
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As it says in the article 28nm to 20nm is 1.9x increase in die and 28nm to 16nm is a 2.0x increase in die, therefore 20nm to 16nm is a 1.05x increase in die.

Basically at 16nm TSMC is going to use their 20nm BEOL and put multigate in the FEOL.

I say multigate because I don't yet know whether they will be FinFETs or Trigate which although many people use the terms interchangably they actually are not the same thing.

krisi
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Re: 20nm costs
krisi   10/2/2013 5:05:21 PM
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thankyou @ScottenJ, makes sense

resistion
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Re: 20nm costs
resistion   10/3/2013 12:42:06 AM
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The double patterning paranoia was apparently a scheme to justify large investments (i.e., EUV) and scare away smaller (i.e., not Intel, TSMC, Samsung) firms.

goafrit
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Re: 20nm costs
goafrit   10/2/2013 8:16:18 PM
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Wait for carbon tubes to redesign this roadmap.  This obsession with smaller feature size is not a roadmap for long haul, it is a marketing message to show innovation. I do not see that value - moving from 22nm to 16nm. I know it was a big deal from 3.3um to 90nm

jamescpwang
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Re: 20nm costs
jamescpwang   10/3/2013 5:08:24 AM
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Compared to 20HKMG, 16FinFET's value is 20% better speed or 35% less power consumption. There's no density advantage migrating from 20nm to 16nm and the Cost per area/die will go up at 16nm. All supply chain members must implement continuous cost cutting program to accommodate the higher cost.

It's a good idea for tsmc by achieving 16nm development with 20nm development as a stepping stone. Combining too many revolutionary BEOL (metal double patterning) and FEOL (FinFET) variables in one development may result in much longer development time.

Significantly revised design flows with so many new design rules to follow (65nm with 800 rules, 20k deck size; 20nm 3k, 80k; and 16nm 3.4k, 100k), so many new simulation corners to signoff (28HPM at 280 corners and 16FinFET 360 corners) and so many analog circuit to redesign (100% redesign at 16FinFET), it's good to have two nodes for designers to migrate smoothly.

It's a big waste if the complicated gate-last HKMG technology has been used in only one node at 28nm, especially for tsmc with overwhelming market share win at the HKMG node.

ScottenJ
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Re: 20nm costs
ScottenJ   10/3/2013 12:41:49 PM
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James

TSMC's gate last HKMG will continue to be used at 20nm and 16nm, it wasn't just for 28nm.

Additional comments relevent to this thread:

The key issue right now it the lateness of EUV which is making shrinks much harder and more expensive. TSMC's 20nm will be a full shrink with some cost reduction, 16nm is essentially no shrink and a big increase in die cost so only customers who need performance are likely to use it. At 10nm - hopefully with EUV we should see a full shrink again with a full cost reduction.

It does look like Multigate is the leading technology for 16nm/14nm and below. FDSOI/ETSOI appears to be a low power/RF niche technology to me.

Please note I say multigate and not finFET. A classic finFET is a fin with gates on both sides. Intel's Trigate is a fin with gates on the top and both sides, that is a significant difference. For Trigate you have to deal with the high electric field at the top corners but you also get to relax the fin width.

For fully depleted operation SOI silicon thickness has to be 1/3 the gate length and that is really hard to do as gate lengths scale down. For finFETs with 2 gates the fin width must be 1/2 the gate length. For TriGate the fin width is 1x the gate length making manufacturing easier.

It will be interesting to see whether TSMC makes a classic 2 gate finFET or a 3 gate Trigate.

rick merritt
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Re: 20nm costs
rick merritt   10/3/2013 1:59:14 PM
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@ScottenJ: Thanks for the i nsightful comments and good future questions for TSMC!

I'll be at IMEC next week and hope for an update on EUV among othewr things.

resistion
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Re: 20nm costs
resistion   10/4/2013 12:49:11 AM
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It looks like one of the 20 nm or 16 nm nodes will be skipped by TSMC customers. But I think the 10 nm node will involve triple or quadruple patterning. See p. 7: http://www.eda-stds.org/edps/Papers/4-4%20FINAL%20for%20Tom%20Quan.pdf

If the quadruple patterning is double the cost but 4x the density from single patterning, it still continues cost reduction. Even with EUV, the energy cost is high, so there is no benefit at that point over multiple patterning.

ScottenJ
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Re: 20nm costs
ScottenJ   10/4/2013 1:41:04 AM
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The cost of EUV is much lower than the cost of quadruple patterning at any reasonable throughput. The energy required for an EUV exposure is more than the energy for a ArFi exposure but is less than the two ArFi exposures plus depositions and etches required for double patterning and is much lower than what is required for quadruple patterning. Quadruple patterning at 10nm could require up to five cut masks and that would be a huge cost problem.

resistion
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Re: 20nm costs
resistion   10/4/2013 1:51:12 AM
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I am not sure where you get the EUV energy (dose) estimates. What you see in publications or the reports from ASML or IMEC (15-20 mJ/cm2) is not going to work in the high-volume manufacturing, with billions of features requiring a certain dose precision. More like 60 and going higher. It makes no practical difference from multiple patterning because, for a smaller node, this dose has to go up, similar impact to increasing ArFi exposures.

any1
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Re: 20nm costs
any1   10/4/2013 9:48:20 AM
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@ ScottenJ writes:

The cost of EUV is much lower than the cost of quadruple patterning at any reasonable throughput.

At some point in the future the cost of EUV could be cheaper than quadruple patterning.  But when will that be?  What throughput is reasonble and what will it take to get there?  I would not make such a blanket statement today.  The whole EUV infrastructure will still be quite expensive in the near term.  And I think there are still too many unknowns today to declare that EUV lithography will be cost competitive by a certain date.  I don't think its guaranteed.  Obviously each company will have to decide what it's costs will be with either scenerio, which will depend on many factors.  Whether or not EUV will be ready for a 10 nm node remains to be seen.

hchan2n
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Re: 20nm costs
hchan2n   10/7/2013 4:52:39 AM
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Hi,

Thanks for commenting on EUV and finFet.

>> "For fully depleted operation SOI silicon thickness has to be 1/3 the gate length and that is really hard to do as gate lengths scale down. For finFETs with 2 gates the fin width must be 1/2 the gate length. For TriGate the fin width is 1x the gate length making manufacturing easier."



Could you elaborate in detail the relationship among gate length, fin width, and trigate / dual-gate?   By "gate length", do you mean transistor width?  Isn't "gate length" also known as channel length?   Transistor width is a function of fin pitch, fin height, fin width, and whether the fin is tri- or dual- gate.  Isn't it?

In figures of IvyBridge Tri-gate 22nm process reported by Chipworks: fin_width(bottom)~=15nm, fin_height~=34nm, and gate length 23.7~24.6nm.  Fin_width(top) seems to be about of 1/2 of bottom.

 

ScottenJ
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Re: 20nm costs
ScottenJ   10/7/2013 10:37:11 AM
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By gate length I mean the gate length not gate width following the standard definition. Gate length is the HKMG gate length between the source and drain along the fin. 

hchan2n
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Re: 20nm costs
hchan2n   10/8/2013 5:15:30 AM
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Thanks for clarifying the meaning of gate length.  I still don't understand:  "For finFETs with 2 gates the fin width must be 1/2 the gate length. For TriGate the fin width is 1x the gate length making manufacturing easier."  Could you describe further?

ScottenJ
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Re: 20nm costs
ScottenJ   10/8/2013 12:26:05 PM
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The whole idea behind FDSOI and Multi-Gate is to create a fully depleted channel in order to minimize off-state leakage.

Simply put a gate only controls a finite thickness.

For FDSOI you have one gate on top of the channel with a buried oxide underneath the channel. The silicon device layer thickness (the thickness of the film under the gate) must be 1/3 the gate length or the gate can't control the channel and achieve a fully depleted device. This is the major scaling challenge for FDSOI, it is very hard to make SOI device layers that thin.

For a FinFet you have a thin fin with two gates, one on each side "squeezing" the channel and the fin width (thickness) can be ½ the gate length and still achieve a fully depleted channel.

For a TriGate you have three gates squeezing the cahnnel from both sides of the fin and the top and the fin width (thickness) can be the same as the gate length and still achieve a fully depleted device.

Basically the more gates you have controlling the channel the thicker it can be and still be fully depleted in the off state.

There are even solutions being explored for the long term with gates on all four sides for even better control.

Please note that in each case the thickness can be smaller but not larger than the specified amount and achieve fully depleted operation.

AKH0
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Re: 20nm costs
AKH0   10/3/2013 12:46:29 PM
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Wondering if the power saving numbers are backed by Si or are just model numbers. Back in 2011 we heard claims of 50% power reduction and what was shown in product was about 20% at high end and almost no change for low power parts.

rick merritt
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Re: 20nm costs
rick merritt   10/3/2013 2:06:02 PM
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@jamespcwang: I don't follow the EDA side closely but you capture the issue of rising complexity for chip designers beautifully with the metrics below:

65nm with 800 rules, 20k deck size;

20nm 3k, 80k; and 16nm 3.4k, 100k)

28HPM at 280 corners and 16FinFET 360 corners and so many analog circuit to redesign (100% redesign at 16FinFET)

 

Wow!


krisi
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Re: 20nm costs
krisi   10/3/2013 12:23:23 PM
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Carbon nanotubes have long ways to go...no need to involve them in this short term discussion

dynamited77
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Show me the 20nm
dynamited77   10/3/2013 2:00:17 AM
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Doesn't look like they got anything at 20nm working above 3ghz, no gen2+ pcie or hdmi. Got to wonder what sort of pll their making, also. Guess they got three more months to actually sell a 20nm this year. BTW, no talk of yield?

jamescpwang
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Re: Show me the 20nm - yield
jamescpwang   10/3/2013 3:07:18 AM
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In the slide "20Soc Value Proposition", demonstrated 20nm 112M HD SRAM nature yield of > 75%. The same nature yield of 16nm FinFET 128Mb HC SRAM.

rick merritt
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Re: Show me the 20nm
rick merritt   10/3/2013 2:08:33 PM
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@dynamited: Good point on apparent lack of 3 GHz IP s far at 20nm.

Many of the major 28nm designs used PCIe Gen 3. Pewrhpas they will skip 20 and go for 16?

daleste
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Re: Show me the 20nm
daleste   10/3/2013 11:14:52 PM
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Not surprising to see TSMC pushing forward to smaller technologies. With the number of wafers they process, they have the volume to push the envelope. The great thing is the number of companies that will benefit from this advancement.

AnySilicon
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FinFET
AnySilicon   10/3/2013 3:14:18 AM
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Seems like FinFET willl be the leading technology for 20nm and below.

resistion
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EUV DP vs. 193i QP
resistion   10/4/2013 10:01:45 AM
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For the 10-14 nm half-pitch, it's going to be 193i quadruple vs. EUV double patterning. Vs. maybe other options like maskless or DSA or imprint or their combo. Tough choice?

ScottenJ
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Re: EUV DP vs. 193i QP
ScottenJ   10/4/2013 11:45:39 AM
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DSA is still pretty early in the development process. It is a very interesting alternative but still a long way off.

The key question really is what throughput is EUV going to hit and when. In the simulations I have run EUV at 50 wph is already less expensive than triple pattering let alone quadruple patterning. ASML is forecasting 88 wph next year so if they meet that EUV could potentially be a 10nm alternative in a year. 

I don't expect EUV to need double patterning at 10nm, certainly not for logic.

resistion
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Re: EUV DP vs. 193i QP
resistion   10/4/2013 12:02:03 PM
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It might be currently 30 targeting 80 WPH for 15 mJ/cm2, which is the current reference dose for a lot of resist characterization. But if the minimum dose needs to be over 60 mJ/cm2, for a chip containing billions of 20 nm contacts or line cuts, then the WPH target is not met. The minimum dose doubles with each successive node.

Zeiss reported  at SPIE 2013 the current EUV multilayer for the optics is limited near 13-14 nm half-pitch, which could be 7 nm or 10 nm logic or in between. So if this part of the infrastructure is not changed in time, it's a limit on EUV single exposure.

ScottenJ
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Re: EUV DP vs. 193i QP
ScottenJ   10/4/2013 12:11:38 PM
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TSMC's 1/2-pitch at 28nm is about 45nm, at the 10nm node you are looking at around 15nm to 20nm, siingle pattern EUV should be fine.

resistion
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Re: EUV DP vs. 193i QP
resistion   10/4/2013 12:44:40 PM
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So EUV SP is basically good for one node and is shot-noise limited even there.

any1
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optimistic projections for EUV
any1   10/4/2013 2:08:02 PM
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Unfortunately the past projections for EUV have always been overly optimistic, so it's difficult for me to believe that all of the known (let alone the ones we don't know about) barriers to successful cost effective implementation of volume manufacturing with EUV lithography are going to be resolved in the next two years.

It seems to me given the current 13.5 nm wavelength, the modest NA allowed by the current reflective optics, optical flare and shot noise, resist edge roughness, and other image degrading factors, EUV with single patterning will be lucky to achieve one useful node.  Then what?  Knowing what we know today we might have been better off taking the hit a couple of years ago and putting more resources into optimizing BEUV (beyond EUV, 6.7 nm wavelength).  It's still possible that after all this time and money 13.5 nm wavelength EUV could ultimately be seen as limited just as  157 nm and X-ray lithography technologies were before and simply abandoned.

Currentsci
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TSMC finFET doping
Currentsci   10/4/2013 5:52:16 PM
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In all these preliminary design releases, has TSMC said anything specific on the methods used to dope the bulk finFETs, including the source/drain contants and extensnions and, most interesting, the junction isolation doping in the fin base regions?  Another key item will be the methods for workfunction tuning of the HKMG stacks.  So, do we wait for Dec and the IEDM talks & discusisons or is anything known already?

rick merritt
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Re: TSMC finFET doping
rick merritt   10/6/2013 1:45:41 AM
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@currentsci: Can anyone answer the doping/HKMG questions?

At the event, TSMC didn't go into such detail in the keynotes and the break out sessions were all from partners.

 

ScottenJ
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Re: TSMC finFET doping
ScottenJ   10/6/2013 11:09:22 PM
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I haven't seen anything specific but TSMC tends to follow Intel's technology path. I would expect the fin Vt to be set by implant and in situ doped raised eSiGe and eSiC Source/Drains. For what it is worth I expect EUV system performance NA, Flare, et . To improve over time and there to be multiple single pattern nodes. An older ASML roadmap I saw included going to a ~6.8nm wavelength around 2018 but I am told by Litho friend that there are lot of issues with that wavelength. Also I am told by my Litho expert friends that the statement earlier in this thread about dose doubling with each node is not correct.

resistion
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Re: dose doubling
resistion   10/6/2013 11:30:59 PM
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Dose doubling comes from feature halving area each successive node but the number of photons cannot be halved, because that would increase the shot noise. The photon number should at least stay the same, but since the feature population is increasing as well, even 6 standard deviations allowed for this noise within a population of a billion may not be enough.

resistion
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Re: higher EUV NA
resistion   10/6/2013 11:38:09 PM
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Ideally, the EUV wavelength would be continued with higher NA but this means larger angles, and the multilayer must be modified from its current status. It could impact the reflectivity and therefore the throughput. So there was also a proposal to increase the mask demagnification from 4X to 6X at least. That's another big change.

rick merritt
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Re: higher EUV NA
rick merritt   10/7/2013 1:48:33 AM
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This has been  a very helpful discussion as I prep for an interview with an EUV expert today at IMEC.

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