Gains Come as Costs, Complexity Rise
SAN JOSE, Calif. -- Taiwan Semiconductor Manufacturing Co. is making steady progress on its next two nodes, bringing advances in performance and low power. The bad news is it's widely expected the latest nodes add less transistor density and more cost than in the past.
TSMC has taped out several 20nm chips and expects to let customers start designing 16nm FinFET chips before the end of the year. By the end of 2014 it expects it will have taped out 25 20nm designs and be far along in work on 30 16nm chips.
Company execs gave a frank and detailed rundown of their progress, especially on the 16nm node at a Silicon Valley event here. TSMC is seen as a bellwether of the chip sector and electronics generally because it is one of the world's largest and most advanced makers of semiconductors. It puts out a whopping 1.3 million eight-inch equivalent wafers each month, some of them now down to 20nm geometries.
Both the 20 and 16nm nodes represent key turning points. The 20nm node is the first to use double patterning, requiring more masks and more runs under an immersion lithography machine. It's expected future nodes at 10nm and beyond could require triple or even quadruple patterning, raising costs again.
The 16nm node represents TSMC's first use of FinFETs, a.k.a. vertical transistors. Indeed, this node basically just adds FinFETs to the existing 20nm process, thus it provides almost no gain in packing in more transistors per area of die, although it does offer benefits in lower power or higher performance.
TSMC execs did not mention the added costs and the reduced density in talks here, and they were not available for interviews afterwards. In past events the execs remained in the hall, answering a few questions for reporters and others, but this time they left the hall directly after speaking.
Nevertheless, TSMC execs read out testimonials about its 20nm process from a handful of key customers. Oracle said it successfully taped out its M7 server processor in TSMC's 20nm node. Xilinx said it used the node for a PLD, and Altera said it is developing its latest serdes in the node. Smartphone chip giant Qualcomm said it is developing both 16 and 20nm design flows with TSMC.
TSMC's long-time chairman Morris Chang (above), 82, did not make the trip to San Jose for this event although he spoke to a crowd of several hundred engineers via a pre-recorded video. Chang's absence rekindled discussion among attendees about the succession plan at the company which has a deep bench of seasoned executives but none with the breadth of experience or clout as the man they refer to as "chairman."
"We see more opportunities, but the window to capture them is getting smaller and smaller, [requiring] heavier investment and greater complexity [so there's a] need to leverage all our expertise," Chang said in his video. "We need each other to be competitive and to win," he told the audience of partners and customers.
The following pages provide details about TSMCs progress at 20 and 16nm. They also provide a look at its ongoing work in 3D stacking technologies seen as an alternative way to gain performance and power benefits at a time when traditional techniques are becoming more complex and costly.
Making Progress at 20, 16 & 10nm
TSMC showed plans for 10nm node in 2015 (above), and said it has started 20nm tapeouts and foresees 16nm tapeouts starting soon (below). Click here to enlarge.
CTO Gives Sun-y Picture
"Moore's Law is getting more expensive and not all specialty technologies need to go on the bleeding edge of Moore's Law technology," said Jack Sun (above), TSMC's vice president of R&D and CTO in a keynote here.
The statement was a somewhat oblique and a rare acknowledgment of the rising costs of CMOS scaling.
The good news is TSMC believes it can offer the full advantages of a new process node with a 10nm FinFET process, including a doubling in the density of logic gates relative to the 16nm node. Designers could start early work in the 10nm process before the end of 2015, Sun said.
The foundry believes it can continue to deliver processes that provide 15 percent compound annual performance gains or 20 percent annual power decreases, Sun said. It also expects volume demand for its new 20nm process will surpass sometime in 2014 the 2012 level of demand it had for its current 28nm process.
That does not necessarily mean the 20nm process will outshine 28nm overall long term. Broadcom and other companies have announced they will not move as many products as fast to new nodes once the higher costs of double patterning kick in at 20nm and beyond.
TSMC's own slides show no major logic density increases from 20 to 16nm, mainly because the 16nm process is based on the 20nm back end. Click here to enlarge.
The need for significantly revised design flows, more masks and double patterning is behind the moves to half-nodes and the -- at least temporary -- lack of density gains. Click here to enlarge.
Foibles of FinFETs
The benefits of TSMC's 16nm node come mainly from its use of FinFETs, vertical transistors long in research and pioneered in commercial chip making by Intel. Cliff Hou (above), vice president of R&D at TSMC, detailed some of the trade-offs FinFETs bring.
FinFETs cause challenges in RC extraction accuracy that now largely have been overcome. However the process still requires somewhat restrictive EM rules to handle its high drive current, an issue TSMC and partners are still working on, Hou said.
In addition, FinFETs offer low voltage operation. However, that can cause difficulties getting accuracy in statistical timing analysis. "Crosstalk still has room for improvement, and working with partners on it," Hou said.
On the positive side, TSMC has new SRAM macros that can shrink the area needed for cache-memory blocks as much as 20 percent, Hou said.
More Foibles of FinFETs
Blocks for 20, 16nm Chips
TSMC's 16nm standard cell offerings will be ready by April, Hou said. The foundry already has completed functional validation of about 300 cells, and a complete library of about 1,000 could be finished by the end of the year.
Three Roads to 3D Stacks
As CMOS scaling grows more complex due to lithography issues, technology for 3D chip stacks is slowly advancing as an alternate route to delivering smaller, faster, cheaper devices. TSMC laid out a set of three 3D processes it is working on (above).
"Billions of transistors can be integrated in this technology with a few hundred thousand microbumps," said Sun.
The latest approach is a so-called wafer-level fan-out that can create parts just 250 microns thick. "That's ideal for future mobile devices," Sun said.
A Lower-cost 3D Option
The latest 3D stacking process at TSMC can handle up to three layers in a 0.5 mm stack. It costs just a penny per mm2 of die area. "That's very attractive for a lot of cost-sensitive apps," Hou said.
By the end of 2013, TSMC aims to support this approach on chips with up to 2,000 pins. It believes it could extend its work to support chips with up to 3,600 pins by the end of 2014. "I think this could be very disruptive for many applications," said Hou.
But it's a whole new approach stacking chips vertically rather than scaling them to newer finer process nodes. So TSMC will offer training on the 3D techniques, Hou said.
Lower cost is music to the ears of chip designers interested in 3D stacks. To date the cost of the approach has been the major limitation to using it.
Big Bucks, Big Bets
TSMC continues spending significantly on R&D and capital equipment. As 10 and 7nm nodes approach, spending is expected to increase yet again.