MIPI, which stands for Mobile Industry Processor Interface, was originally conceived as a low-power interface intended to interconnect functional units (e.g., camera sensors and displays) within handsets.
The popularity of MIPI has mushroomed in recent years -- many component suppliers have adopted the standard and debuted a variety of MIPI-enabled devices, including camera sensors, displays, and application processors. Although a strong interest to tap into the mobile market is the primary reason for such a move, the MIPI trend has caught the attention of designers building systems for non-mobile markets, such as automotive, industrial, and medical. The rationale for this is that MIPI-enabled products are intended for high-volume mobile markets and so they are bound to be cheaper.
This has led to an interesting dilemma. Since MIPI as an interface was never intended to serve non-mobile applications, interfacing to FPGAs was never made a priority. This makes perfect sense, since the majority of FPGAs are not well-suited for use in high-volume mobile devices. On the other hand, FPGAs are quite common in medical, industrial, and automotive applications. The end result is that the lure of using low-cost MIPI-enabled devices and the need to connect them to FPGAs has forced designers to look for bridging solutions.
MIPI's D-PHY, which involves a mix of analog circuitry and digital logic, uses SLVS (scalable low-voltage signaling) signals. Meanwhile, FPGAs from vendors like Altera and Xilinx support LVDS (low-voltage differential signaling) and LVCMOS (low-voltage complementary metal oxide semiconductor) signal levels, but they can't directly accept or drive SLVS voltage levels.
In addition to this fundamental mismatch, MIPI signals support two distinct signaling modes. One mode is used for high-speed data streams (up to 2.5 Gbit/s), while a slower mode is used to transport commands. In order to interface to an FPGA, both of these modes must be supported. An effective bridge must be intelligent enough to distinguish between these two modes and to make both streams available to the FPGA. At the same time, the bridge must also handle the voltage level-shifting required to adapt MIPI SLVS signals to the LVDS and LVCMOS signals used by FPGAs.
There are a number of ways to tackle this problem. For example, Meticom offers a family of bridge ICs that enable seamless connection of MIPI D-PHY or CSI-2 devices to FPGAs. This offering consists of single-channel receiver and transmitter chips (the MC20001 and MC20002, respectively) along with their five-channel counterparts (the MC20901 and MC20902). Five-channel devices come in handy since a D-PHY interface can support up to four data lanes and one clock lane.
The illustration below is an application diagram depicting the connection of an FPGA to a MIPI-enabled camera (D-PHY source) and display (D-PHY sink).
Bridging between MIPI-enabled devices and an FPGA
(Click here to see a larger, more detailed image.)
It's important to note that the solution shown above does not require discrete voltage resistor dividers and is quite elegant when it comes to simplicity and component count. Furthermore, Meticom's bridge devices shown above have built-in intelligence to discern between high-speed and low-speed traffic (i.e., data vs. commands) and can automatically route them to the relevant inputs and outputs of the FPGA.
Implementing a MIPI bridge using discrete components is certainly possible and will most likely yield to the lowest BOM cost. On the other hand, a discrete solution is messy and time-consuming to design. Such a solution is bound to require a large number of discrete components and will make testing and assembly difficult. Using application-specific standard part (ASSP) bridge devices -- such as those from Meticom -- has a number of advantages as summarized below:
- Standards Compliance: Using merchant bridge chips like the ones from Meticom shifts the burden of compliance testing from designers to the IC vendors. IC vendors have spent significant time and resources to assure full compliance to the standards set forth by the MIPI Alliance. There is no question that discrete solutions can be made to be compliant, but at what cost?
- Power Dissipation: In discrete implementations of MIPI bridges, the required voltage level-shifting can be achieved using resistor dividers, but such dividers are not power efficient and they will certainly tax the power dissipation budget of the system. Merchant solutions, by comparison, alleviate this problem and are far more power efficient.
- Speed: Discrete solutions are feasible up to speeds of 1Gbps but are not recommended for faster interfaces. Merchant bridge ICs can easily cover speeds approaching 2.5 Gbit/s and beyond.
- Bill of Material (BOM) Count and Ease of Assembly: Dozens of discrete components are needed to implement an effective MIPI bridge. This will certainly have a negative impact on the manufacturing logistics and system reliability.
Please visit Meticom's website for more information on MIPI-to-FPGA bridging solutions.