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ARM Unveils New Architecture for Automotive

10/23/2013 07:55 AM EDT
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R_Colin_Johnson
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Automotive Hypervisors for Safe Add-ons
R_Colin_Johnson   10/23/2013 9:33:02 AM
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The new ARMv8-R virtualization with its "bare-metal" hypervisor mode should prove to be really popular among software developers wanting to add-on functionality while maintianing all the safety that automotive demands.

junko.yoshida
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Re: Automotive Hypervisors for Safe Add-ons
junko.yoshida   10/23/2013 9:43:29 AM
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Exactly. I agree, Colin. As I understand it, this has been a big headache for them.

Similarly, this should make it easier for SoC design, according to the Linley Group's Kevin Krewell.

 

Bastian.Schick
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Re: Automotive Hypervisors for Safe Add-ons
Bastian.Schick   10/23/2013 12:08:52 PM
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Frankly, I see this announcement of ARM just as a marketing blob. They want to ride the A7 wave.

Let me reason why:

- Todays Cortex-R4 offers already the protection mechanisms needed to run safety and non safety software on the same chip (see TI's TMS570, RM4x).

- No one needs 64bit unless he wants to run Android for the multimedia stuff inside a deeply embedded device.

- The "protection" needed is more a bus thing then a CPU thing which is already implemented in ARM devices or PowerPC devices (see FSL Quoriva).

- Do we really want the breaking system software run on our radio? (Ok, this is not an rational argument)

 

So what is now the reason for this "new" architecure?

Wilco1
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Re: Automotive Hypervisors for Safe Add-ons
Wilco1   10/23/2013 1:10:14 PM
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This is the v8 version of the v7-R architecture. So it is indeed compatible with existing cores like Cortex-R4 but adds new features as well, such as the Hypervisor and support for running Linux. Note v8-R is not 64-bit.

See http://arm.com/files/pdf/ARMv8R__Architecture_Oct13.pdf for all the details.

Bastian.Schick
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Re: Automotive Hypervisors for Safe Add-ons
Bastian.Schick   10/24/2013 1:51:00 AM
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Ok, reading this document shows really some improvements over v7R.
But it again makes me wonder why ARM differs -A and -R but now they mix -A and -R with the v8-R only that there is no 64bit support (which I do not miss) and no support for the new ISA with 32 registers (which I miss).
Granted, todays feature rich (overloaded?) OSes will not run on a R or M CPU, but on the other hand, an RTOS very well runs on an A one.

I really wonder: Do the ARM ISA developers talk to (RT)OS designers asking what they think an ISA needs? I mean, how come an Cortex-A CPU does not have integer divide? (Ok, now going off-topic...)

So lets wait for the first dual-core v8-R (no more Cortex I guess) CPU.



Wilco1
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Re: Automotive Hypervisors for Safe Add-ons
Wilco1   10/24/2013 8:03:05 AM
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The R variant of the architecture has always been something of a middle ground, with some -M features and some -A features. That's just what the RTOS people seem to need.

If you want 32 registers then you do want 64-bit but use 32-bit pointers to avoid the overhead of 64-bit pointers. For x64 there is already a Linux ABI with 32-bit pointers, so I bet there will be one for ARM64 as well.

The issue with running an RTOS on an -A core is that interrupt latency is much higher on fast OoO cores with large caches. So you lose the R in RTOS. The -R cores have special features to keep interrupt latency low (although to get the lowest interrupt latency you have to use an -M core).

All Cortex-A cores since A15 do have integer divide. The latest QC and Apple cores do have divide as well.

 

 

Bastian.Schick
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Re: Automotive Hypervisors for Safe Add-ons
Bastian.Schick   10/24/2013 8:25:42 AM
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The issue with running an RTOS on an -A core is that interrupt latency is much higher on fast OoO cores with large caches. So you lose the R in RTOS. The -R cores have special features to keep interrupt latency low (although to get the lowest interrupt latency you have to use an -M core).

Actually, I'd say no. There are a lot of CPUs arround with cache which are used in realtime enviroments (like all the automotive PowerPCs).

All Cortex-A cores since A15 do have integer divide. The latest QC and Apple cores do have divide as well.

The thing is, Cortex-R4 has it, but e.g. ZYNQ Cortex-A9 does not have it as it is "optional".

Encoding T1 ARMv7-R, ARMv7VE, otherwise OPTIONAL in ARMv7-A
SDIV<c> <Rd>, <Rn>, <Rm>


and


In an ARMv7-A implementation that does not include the Virtualization Extensions, the implementation of SDIV
and UDIV in both instruction sets is OPTIONAL, but the architecture permits an ARMv7-A implementation to not
implement SDIV and UDIV.


So what? I really wonder, what goes on in the brains of architecture developers (and as it is optional: implementers) :-(

Wilco1
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Re: Automotive Hypervisors for Safe Add-ons
Wilco1   10/24/2013 8:50:01 AM
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Well I'd be surprised if those PowerPCs had an interrupt latency of ~10 cycles. Cortex-R cores are used in hard realtime tasks like flying the heads of a HD. Typically when you have caches latencies go up to hundreds of cycles. This is due to having many outstanding cache misses and writebacks in flight - you can't just drop those on an interrupt as you end up in an inconsistent state...

All new cores like Cortex-A7, A12 and A15 have division. Cortex-A8/A9 don't have divide as division was introduced well after they were finished. I agree it's not ideal but then again around 10 years ago, when I talked to an ARM hardware guy and asked how fast he could implement division on something like ARM11, his answer was "about 40 cycles". I then said "well my software division easily beats that with an average time below 30 cycles, so don't even bother". It seems that after the introduction of Cortex-M3 with its amazingly fast division hardware designers made division fast enough on higher-end cores as well!

 

Denis.Giri
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Re: Automotive Hypervisors for Safe Add-ons
Denis.Giri   10/24/2013 3:57:00 AM
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Honestly, I'd like to see more information on how they deal with the virtual adressing issues of the richOS...

VMSA usually assumes a MMU, but ARMv8-R apparently only has a MPU (PMSA instead of VMSA)

Wilco1
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Re: Automotive Hypervisors for Safe Add-ons
Wilco1   10/24/2013 8:25:16 AM
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It's very simple: v8-R supports both VMSA and PMSA, so it has an MPU and MMU. Otherwise you wouldn't be able to run standard Linux.

junko.yoshida
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Licensees?
junko.yoshida   10/23/2013 9:47:29 AM
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Although ARM's announcement today came with no names for potential licensees for the new v8-R architecture, Nvidia's comments in the story make it clear that the hardware-supported virtualization feature, enabled in the new architecture,  is something very much in demand by chip companies hot to trot for developing automotive platform.

R_Colin_Johnson
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Re: Licensees?
R_Colin_Johnson   10/23/2013 9:58:24 AM
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Yes indeed. I imagine NVIDIA and other chip companies are hot to  get into the lucrative automotive space, and ARM is giving the the foot-in-the-door they need. The competition should bring many benefits to the consumer--new features, capabilities and options.

rick merritt
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Re: Licensees?
rick merritt   10/23/2013 12:43:53 PM
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I can see this intensifying competition in microcontrollers where there's a split between many ARM licensees and the Microchips and Renesas-es.

Real time was a last bastion for some of these guys

sanjaac
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Re: Licensees?
sanjaac   10/23/2013 1:46:19 PM
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Rick,

Maybe you are not well informed, which would be really surprising, but Renesas has long been an ARM licensee in the Automotive -namely Infotaiment segment- market, with R-Car family (http://am.renesas.com/applications/automotive/cis/cis_highend/index.jsp). A quick excerpt, excluding SuperH-only devices:
  • R-Car E1: ARM® Cortex™-A9 533 MHz, 1330 DMIPS
  • R-Car M1A/S: ARM® Cortex™-A9 800 MHz + SH-4A core 800 MHz (M1A), 3760 DMIPS
  • R-Car H1: ARM® Cortex™-A9 1 GHz x 4 + SH-4A core 11760DMIPS
  • R-Car M2: ARM® Cortex™-A15 × 2 + SH-4A core over 12000DMIPS
  • R-Car H2: ARM® Cortex™-A15 × 4 + Cortex™-A7 × 4 + SH-4A core over 25,000 DMIPS

A few more details of the R-Car H2: http://am.renesas.com/press/news/2013/news20130325.jsp

So, no really clear where is the split you mention.

Or is it maybe, because some MCU vendors - Renesas for instance- also have automotive devices, more dedicated for Real Time tasks, like the RH850 (http://am.renesas.com/products/mpumcu/rh850/index.jsp?campaign=gn_prod) or V850 (http://am.renesas.com/products/mpumcu/v850/sub/automotive.jsp) families, among others, and now with ARM's announcement we see a marriage of RealTime and Non-RealTime tasks on a same device?

But in any case, it is not an ARM or not-ARM split, at least not in Renesas case, neither in Industrial nor in Automotive fields.

Cheers.

rick merritt
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Re: Licensees?
rick merritt   10/23/2013 9:34:17 PM
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Good point, Sanjaac. Renesas is playing both sides of the fence although I believe its propritary MCU architecture is one of the most widely used.

junko.yoshida
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Re: Licensees?
junko.yoshida   10/24/2013 12:27:03 AM
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From what I understand, Renesas does use ARM cores more often in multimedia applications -- SoCs for in-vehicle infotainment , or Advanced Driver Assistant Systems.

prabhakar_deosthali
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prabhakar_deosthali   10/23/2013 12:09:33 PM
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This looks to be a path breaking architecture .

I am just curious to know whether this will this bring more standardization in the automotive software development process and may it more individualistic.

For security certification it may be advisable to have some kind of standardization in the software modules and their integration process.

With driver-less cars now on the horizon this is all the more important an issue

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