SAN JOSE, Calif. — Samsung and SK Hynix will give a peek into the future of low- and high-end memory chips in separate papers at the International Solid-State Circuits Conference (ISSCC) in San Francisco in February.
Samsung will demo low-power DDR4 SDRAMs for smartphones for the first time at ISSCC. SK Hynix will give the first disclosure of its High-Bandwidth Memory, a stack of four memory chips fueling next-gen comms, graphics and server chips.
Samsung will describe 8 Gbit LPDDR4 chips running at 3.2 Gbits/second/pin at 1.0V. The chips support error correction codes and sub-volt operations and are made in a 25nm DRAM process.
The devices mark the highest data-rate and density and lowest supply voltage reported to date, said ISSCC organizers. They are expected to start replacing today's LPDDR3 chips sometime next year in smartphones and other systems.
In a separate paper, Samsung will describe the smallest SRAM cells reported to date. The 0.064mm2 cell is made in a 14nm FinFET processusing novel read/write assist schemes.
For its part, SK Hynix will disclose details for the first time of its High-Bandwidth Memory (HBM). The 8 Gbit part uses four die stacked using through silicon vias to deliver 128 GBytes/second at 1.2V using a 29nm DRAM process. The device supports eight channels and 1,024 total I/Os.
Rival Micron has been vocal about its plans for a similar memory stack called Hybrid Memory Cube, aimed at feeding high-end comms, graphics and server processors.
Micron is now sampling a 4 GByte HMC stack delivering 160 GByte/second. Memory stacks "are expected to create many new applications requiring higher bandwidth in future memory sub-systems," said ISSCC organizers.
Separately, Intel will show at ISSCC a Gbit embedded DRAM running at 2 GHz at 1.05V and made in its 22nm logic process. A 128 Mbit macro has a density of 17.5Mbits/mm2 using a cell size of 0.029mm2.