SAN JOSE, Calif. -- Intel will describe its Ivy Bridge-class processor for mainstream servers for the first time at the International Solid-State Circuits Conference in February. Also at ISSCC, Applied Micro will reveal details of the first 64-bit ARM server SoC, targeting low power so-called microservers.
The two chips target separate server markets, but still underscore the new competitive dynamics in cloud computing where power consumption has become a top criterion.
Intel's paper is expected to be its first technical presentation of Ivytown, its 22nm Xeon processor. The Ivy Bridge generation marks Intel's biggest effort to date to lower power of its x86 core.
Ivytown packs 15 cores and 37.5 Mbytes shared L3 cache on an enhanced ring. The 4.31 billion transistor chip supports a one-PLL per column clocking structure and a multimode memory interface, according to an abstract of the ISSCC paper released November 5.
For its part, Applied Micro will detail X-Gene, a server-class ARM SoC integrating four 4.5W dual-core processors running at 3.0 GHz in a 40nm TSMC process at 0.9V. The custom ARMv8 cores sport a four-instruction, out-of-order superscalar pipeline.
"These processors represent a new level of performance, integration, and innovative circuit techniques to deliver significantly increasing performance and capabilities," said organizers of the ISSCC microprocessor track.
Separately, IBM will present a paper on Power 8. The 12-core server processor with 96 Mbytes of on-chip L3 cache was described at Hot Chips in August. Similarly, AMD will further detail its high-end x86 core called Steamroller initially implemented in 28nm technology and also previously announced.