PORTLAND, Ore. -- The world's first 3D compound-semiconductor FinFET to integrate III-V and silicon materials on the same 300-millimeter wafer has been claimed by Imec -- the Leuven, Belgium-based microelectronics research center. Imec's process, if adopted by its partners, aims to continue CMOS scaling at seven nanometers and below, as well as enable hybrid CMOS-RF and CMOS-optoelectronics.
As silicon devices scale down to atomic-scale limits, they are running out of ways to increase performance and lower power consumption. By integrating higher performance materials with silicon, such as III-V transistor channels that provide higher carrier velocity and higher drive current, these hybrid semiconductors aim to enable continued scaling beyond the capabilities of silicon alone.
World's first III-V FinFET transistor fabricated on a 300 mm silicon wafer uses fins made from indium phosphide capped by indium gallium arsenide. (SOURCE: Imec)
Intel and others are already working on experimental compound semiconductors that combine III-V materials like indium gallium arsenide (InGaAs) and indium phosphide (InP) with traditional silicon substrates but have been challenged by the atomic lattice mismatch between the materials. However, Imec claims to now have demonstrated a wafer-scale process, combining aspect-ratio trapping of crystal defects with trench structuring and epitaxial process innovations, that can successfully replace the silicon fins on a 3-D finFET with InGaAs and InP while accommodating almost an eight percent lattice mismatch.
"Basically we go through the FinFET process up to the point where the fins are formed, we then remove the silicon from selected fins using a special etch process close to the bottom of the fin, where we etch patterns to allow for the III-V to grow and absorb the defects," Aaron Thean, director of the Logic R&D at Imec told EE Times. "Then we put the III-V material there, starting with indium phosphide, which absorbs close to an eight percent lattice mismatch and eventually grows to the very top, where we recess again the indium phosphide and regrow the top part with indium gallium arsenide."
According to Thean, Imecs partners have asked it to further develop the technology for possible deployment at the seven-nanometer node circa 2016-to-2018. Imec's CMOS development partners, who will have access to its process, include Intel, Samsung, TSMC, Globalfoundries, Micron, SK Hynix, Toshiba, Panasonic, Sony, Qualcomm, Altera, Fujitsu, nVidia, and Xilinx.
— R. Colin Johnson, Advanced Technology Editor, EE Times