Meanwhile, Samsung is working with what it calls a "10-nm-class" triple-level-cell NAND flash chip. This is just another way of saying 1x nm NAND flash; in this case, TechInsights lists the Samsung chip as being fabricated using a 16-nm process. Samsung is shipping 128-Gb chips for use in solid-state drives aimed at the enterprise storage market. By leveraging its 20-nm production lines for the new chips, the company expects to boost manufacturing yields by roughly 30%. Based on the toggle DDR 2.0 interface, the devices support 400 MB/s data transfer rates.
Is the tech insights article new? The information seems disconnected with other reports. Example is actual definition on 19nm was changed by toshiba. Remember there is both an x and a y :-). Samsung nodes have been multiple between 26nm and 19nm (per techinsights).
Thanks for the story...this is a good list of what each memory vendor has been doing and are up to. A good summary. I wish I could have seen photos of where all those chips are being used (applications), rather than actual memory chips (which, you know, look kinda same)
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.