HUNTSVILLE, Ala. — The latest offering from Digital Core Design (DCD) is the DHDLC soft IP core. Optimized for use with a wide variety of 8-, 16-, and 32-bit MCUs, the DHDLC controller is designed to control HDLC/SDLC transmissions.
Developed by IBM, SDLC (Synchronous Data Link Control) is a communication protocol used at the data link layer of computer networks. Meanwhile, HDLC (High level Data Link Control) is a standard adopted by the International Organization for Standardization (ISO) that was created out of SDLC. Another way to look at this is that SDLC conforms to HDLC protocol requirements, but contains a more precise definition on the modes of operation and is more restrictive.
The DHDLC controller from DCD off-loads the main MCU by handling low-level HDLC/SDLC features, such as bit-stuffing, address recognition, and CRC computation. Like all DCD IP cores, the DHDLC is technology independent, suitable for both ASIC and FPGA implementations. Click Here for more information on the DHDLC controller soft IP core.
— Max Maxfield, Editor of All Things Fun & Interesting