Xilinx has just announced the availability of its 20 nm portfolio of All Programmable UltraScale devices, along with documentation and Vivado Design Suite support. (See also Xilinx Announces 20-nm FPGA/SoC Devices.)
As I reported earlier this year in First 20nm UtraScale ASIC-Class FPGA From Xilinx, only the Zynq, Kintex, and Virtex families are being brought forward to the 20 nm technology node with the UltraScale architecture; the Artix family will continue to "hold the fort" at the 28 nm technology node.
Also of interest is the way in which different types and levels of functionalities are being assigned to the UltraScale incarnations of the Kintex and Virtex families, as illustrated below:
In the case of the number of logic cells (the numbers shown in the above image should be multiplied by 1,000), the amount of block RAM, and the transceiver bandwidth, the Virtex UltraScale devices boast more than their previous generation Virtex 7 counterparts and -- not surprisingly -- more than their Kintex UltraScale cousins. What may be surprising to some is the fact that Virtex UltraScale devices contain fewer DSP slices than previous-generation Virtex 7 devices and latest-generation Kintex UltraScale devices.
The folks at Xilinx explain this by saying that everything they are doing is being driven by their customers and from an application perspective. For applications that require raw signal processing power, the ideal solution will be the Kintex UltraScale family with a peak DSP performance of 8,180 GMACs. The Virtex UltraScale family still offers a very respectable peak DSP performance of 4,268 GMACs, but this family's focus is more on logic capacity, memory capacity, and transceiver bandwidth.
Speaking of logic capacity, memory capacity, and transceiver bandwidth, the Virtex XCVU440 All Programmable 3D IC offers 4.4 million logic cells, 89 Mbits of RAM, and 2.6 Tbit/s of bandwidth, along with a wealth of other features such as 1,456 GPIOs and three 100GE MACs implemented as hard IP cores.
This is where things start to become really interesting. The folks at Xilinx say that the Virtex XCVU440 All Programmable 3D IC offers twice the capacity (in terms of logic cells) of its previous largest device at 28 nm (the Virtex-7 2000T) and 4 times the capacity of anything else available on the market. They also say that the Virtex XCVU440 All Programmable 3D IC provides the equivalent of 50 million ASIC logic gates. The reason this is of interest is that the Virtex-7 2000T was said to provide the equivalent of 20 million ASIC logic gates. So, if the XCVU440 provides 2 times the logic cells of the Virtex-7 2000T, how can it offer 2.5 times the number of equivalent ASIC gates? The answer is a combination of three things: the UltraScale ASIC-class architecture, the Vivado ASIC-strength design suite, and the UltraFast design methodology.
The UltraScale ASIC-class architecture features next-generation routing technology that provides a substantial increase in routing resources. It also features ASIC-like clocking that scales with the device, balances skew, and offers tremendous flexibility with regard to clock placement. Of particular interest is the way in which the UltraScale routing architecture is co-optimized with Vivado, resulting in a significant increase in logic cell packing density. In turn, this leads to shorter wire lengths, higher logic cell utilization and performance, and lower overall power consumption. It's the higher logic cell utilization that accounts for the fact that the Virtex XCVU440 All Programmable 3D IC provides the equivalent of 50 million ASIC logic gates.
Also of interest is the UltraFast design methodology, which is based on a single, unified data model. The UltraFast design methodology moves the majority of the design iterations to much earlier in the design cycle, increases the quality of results (QoR), and dramatically speeds the overall design process (Xilinx says the UltraFast design methodology offers "predictable success in weeks, not months").
Virtex UltraScale devices will begin shipping in the first half of 2014. Click here to learn more about the UltraScale architecture; click here to discover more about the UltraFast design methodology; and click here to see the UltraFast design methodology guide.
— Max Maxfield, Editor of All Things Fun & Interesting