WASHINGTON, D.C. — The job of making advanced chips and finding ways to collaborate on the work is getting tougher, according to a panel of veteran semiconductor researchers who gathered just outside the International Electron Devices Meeting in Washington last week.
Moderator David Fried, chief technologist of Coventor, a supplier of 3D modeling and simulation software, asked panelists to describe the biggest technical challenges they face as well as the key challenges to keeping their projects on schedule. The latter question is critical, given the growing industry perception that the pace of chip scaling is slowing. That is making it harder for IC makers to push designs based on ever-shrinking geometries out the door.
Among the technical challenges mentioned by several device designers was managing growing complexity at smaller geometries. Brian Greene, an IBM senior engineer in charge of its 14 nm FEOL architecture, cited density scaling and incorporation of new epitaxial materials along with adoption of new device architectures.
Samsung Electronics' Sean Lian, who oversees its 7 nm design efforts, noted that "traditional brute force scaling is no longer possible" at the 7 nm node. Lian, among others, stressed delays in critical tools like extreme ultraviolet (EUV) lithography. Hence, Lian said, Samsung's 7 nm approach is "EUV agnostic."
EUV lithography delays and cost growth at advanced geometries also were cited by Andy Wei of Globalfoundries. Wei said the semiconductor industry's ecosystem needs to be changed to minimize the growing list of technical challenges. The EDA industry "needs to help out to reduce some of these difficulties," Wei noted.
Laith Altimime, director of CMOS technology and design at the IMEC manufacturing technology consortium, also stressed the difficulties of managing a growing list of design variables ranging from an emerging "power crisis" to implementing new device architectures and materials.
The Belgium-based group has been leading efforts to encourage greater semiconductor industry collaboration. Altimime called for leveraging the chip industry's full ecosystem in order to tackle key technical challenges, or what IMEC refers to as "the sum of minds."
Coventor's Fried noted that a fragmented semiconductor industry often moving on parallel technology tracks -- FinFETs versus FD-SOI, for example -- makes greater collaboration difficult. "Everyone is willing to collaborate as long as they collaborate on what [they] want," he said.
The panelists did not disagree, offering several tongue-in-cheek collaboration models that included the pooling of resources to form the semiconductor industry's version of the OPEC cartel, the "Organization of the Semiconductor Exporting Countries."
Fried suggested instead that industry collaboration should focus on technology challenges that so far lack viable solutions. Once those issues are identified, he said, "we can put our money where our mouth is."
In theory, increased industry collaboration in research areas like materials and better EUV sources would help address unrelenting schedule pressures. "It's kind of a chicken race," said Wei of Globalfoundries. "Everyone has their two-year schedule" at each new node.
More telling was Wei's troubling observation that "things are really slowing down [at advanced chip nodes] but no one wants to admit it."
That reality is emerging as the learning curve for design engineers grows shorter. Hence, IBM's Greene said the biggest challenge for him is "how much we can learn in the [shorter] time we have."
— George Leopold, former news editor of EE Times, is a science and technology writer in Washington, D.C.