Even though the market is very well served today, Intel has a lot of muscle. I expect that they can take a big portion of the market, but they may not be the best fit for the job. We will watch as the market changes.
The natural conclusion is that Intel will reduce its profit margins considerably to be able to compete. If that trend continues, earnings per share will go down and shareholders will start to question the current strategy. I personally do not think this is sustainable.
There's no question Intel is sdoing everything it can to get into this market as aggressively as possible. I am not sure they will be limited to an eight-core offering though. It seems to me that their product lineup will span as far and wide as they can possibly get it to. They won't be giving up their edge in traditional x86 platforms anytime soon either.
The competition will come down to cost-performance ratio. Cost will cover daily operational cost. It means power consumption of the server (not just the CPU). Performance will include not only MIPS but also how many VMs and services can be run on a single server.
Is there a comparison study of x86 vs ARM? Ideally, a benchmark study.
Current C2xxx (Avoton/Rangeley) line include octa, quad and dual core offerings.
Some design groups are considering greater than eight core micro server processors on the interconnect power saving and blade density. The issue with greater than eight core include fabrication yield and device reliability; mean time between failure. And from a system perspective managing concurrency across up to 24 cores which some propose as the upper limit.
Cloud shops moving to disaggregated rack seek low cost and high density. When a micro blade fails the cloud provider wants to hot swap replace. This raises a concern with multi core processors when a single core fails and the entire array gets pulled and tossed. To the extent a few bad cores can be mitigated by VM seems a possibility, but is beyond the knowledge reference of this analyst if and how so.
Because these are complicated devices sought by cloud providers, for not enough margin from their design producers or design fabricators, device's cost : price ratio supporting design producer margin and development into tomorrow becomes a joint concern.
This analyst believes a standard body might be established focused on failure analysis of multi core blades. With the objective of rating mean time between failures sufficiently to price justify, to the cloud provider, supporting an adequate level of margin for the design producer to justify their continued effort in research and development.
Where cloud providers are concerned with substantial failure of a processing array, which they attempt to secure at the lowest possible price, failure assessment delivering MTBF for life expectancy becomes one means too justify a single multi core processor's adequate economic profit offer price.
For Intel C2xxx quads and duals are not a unique mask set but recovered or disabled. Intel offers less than an eight core offering and will certainly sell less than an eight core offering. The issue for Intel recovering or disabling the eight core device holds a cost that results in overall margin loss across the full production run.
Simply stated if Intel produces 100% of C2xx run as eight core device the average 1,000 units price would be $160.50. Average marginal revenue gain for producing a single octa device would be $140.50. And the design production cost approximately $20 per unit on a good fabrication day. Full Run Revenue at 1,000 unit price for 100% octa cores could be up to $2,514,453,669.
Noteworthy the marginal cost per mm^2 of dice area for Haswell and Xeon 26xx v2 design production is higher than $0.20 per mm^2 of dice area. Cost increase is attributed to the number of Haswell experimental design failures that impact full run sunk cost. For Xeon Ivy refresh the shear size of the dice means even on a good fabrication day the cost per mm^2 for large dice will be greater than small dice.
Economics suggest Intel's design production cost currently averages $0.38 per mm^2 of dice area; low of $0.15 and high of $0.68. During the 1990's one measure for estimating Intel cost is the low price offering within any run. The axiom does not necessarily apply today, however, is still one measure to check against when estimating Intel design and production cost per unit of devices.
Now back to the overall cost impact of recovering or disabling C2xxx from eight to four or two cores. Recovering or disabling comes with a cost. To produce 15,666,387 C2xxx bin split 46% octa, 27% quad and 27% duals delivers average weighed price of $108.69.
This analyst believes AWP is actually higher, $121 to $127, which is a 6 core mouse trap Intel deploys to limit competitors from producing a hexa core competitive replacement, missing from Intel's C2xxx product line up. Where $121 to $127 is Intel's bundled sales package price for the 8/4/2 core 'take it or leave it' package deal. To the extent Intel does not offer a six core device suggests there is yield failure across all eight core C2xxx production.
Having recovered or disabled the bad octa devices, for sale as quads and duals, Intel's marginal cost of production is still approximately $20 for a 100 mm^2 octa device. But now the marginal revenue per device is down to $88.53. In this example Intel gives up $71.97 in revenue for each disabled device to produce the quads and duals.
Full run revenue impact across the production of 15,666,387 total devices of which 42%, or 6,579,883 are quads and duals, is $1,702,823,241 or ($811,630,428) less. That is why Intel has an incentive to sell only the eight core device. Intel cost of producing disabled or recovered quads and duals from the octa total reduces revenue at a cost increase of $473,554,146. This brings the actual design production cost of C2xxx quads and dual up to just under the product lines price low of $43 or cost plus $6 to $8. To the extent that octa yields are less than 46% means some of C2xxx production, likely the duals, are sold at cost. Or bundled in as freebee.
Perhaps Intel did define the term microserver, but not the drivers behind it and it's natural existence today. Just look at current cost and power requirements in server infrastructure, the shrinking bang for the buck being realized by purchasing the latest, highest-power server processors for current workloads, and the increasing availability of SOC-based processors with enhanced IO and various heterogeneous compute engines. Intelligent scaling is sorely needed that makes use of these growing and different features, not just brute force as has been the mantra in the past.
@Fonya: Give Intel some credit for radically scaling back the power of Xeon and Atom cores in servers...and fir being the the first to ship a custom low-power SoC for servers. Atom's there today, ARM not yet really.
Clearly there are many companies offering ARM SoC's in this space that deserve some sort of credit. But Intel can still leverage its advantage in the server processor market in general in order to take those companies on in microservers in the long-run. Calxeda is a good example of the pressure and the difficulty that those companies face, given its recent fate.
@Rick: Give Intel some credit for radically scaling back the power of Xeon and Atom cores in servers...and fir being the the first to ship a custom low-power SoC for servers. Atom's there today, ARM not yet really.
Intel already had low power designs in the ATOM line, so extending the technology to servers wasn't a big stretch. And Intel could read the tea leaves, and see that as server density multiplied, power and cooling requirements would become an increasing concern.
Atom was intended for smaller devices, like smartphones, tablets, and netbooks, where battery lie was the scarce resource, but it hasn't been competitive with ARM in the smartphone and tablet space, where the huge growth has been.
It's gambling it can get a lead in servers, because the server space is basically 64 bit, and ARM doesn't yet have a 64 bit design that might be used in servers.
It will be interesting when 64 bit ARM cores become available in silicon to use in server applications. In 32 bit processors, ARM has been more power efficient than Atom. Will that continue in 64 bit machines? If it does, and overall performance of ARM based servers is good enough to meet customer requirements, Intel's lead may be transitory.
@docdivakar: I hope what you say abou 64 bit ARM cores becomes a reality in 2014 because the data center applications really do need that from all perspectives.
I'm sure ARM, Ltd is head down and plowing ahead to bring it about, but I don't know if 2014 is feasible. First, ARM has to have a set of 64bit designs. Then vendors have to implement them in silicon. How fast can that happen?
I see a fairly enormous market where raw performance is not the key factor. Google and Facebook data centers are examples: scale by adding more servers. Sheer performace of any individual server won't be as critical. What will be critical will be server density, with associated power and cooling requirements. Power efficiency needs to be superb. Performance merely has to be "good enough".
If I'm the Google exec in charge of data center build-outs, I'm probably salivating over the potential of 64 bit ARM designs if the power efficiency is in line with the 32 bit units. An Intel processor may be faster, but I don't care. What I do doesn't generally require the fastest server, and faster chips will be more expensive with higher costs per CPU, as well as greater power requirements.
Intel sees an opportunity to get an early jump on low power 64 bit server designs. The key for Intel will be increasing power efficiency even further. What I've seen thus far is that 32 bit ARM designs beat Intel Atom designs with performance roughly comparable. If 64 bit ARM designs have the same advantage over low power 64 bit Intel designs, Intel has an uphill battle.
Intel might find itself split internally, with their state of the art foundries that generate revenue shipping silicon advocating licensing ARM cores, because they see a better market for the silicon thay make if they have ARM designs to sell. (Intel used to make ARM chips before they sold the division to Marvell, so there's precedent.)
Of course, if your observation is correct and Intel's 32-bit core designs are behind ARM's in terms of pwerformance, that does not bode well for the race in 64-bit designs. Still, getting there first and having the raw performance advantage in general with faster CPUs gives Intel a bit of breathing room.
ARM already has finished 2 64-bit designs, Cortex-A53 and A57, which will appear in products mid 2014. X-Gene will be available before that - initial versions use 8/16 4-way OoO cores at 2.4GHz, so clearly aiming for top performance (faster than A57). It will be interesting to see how they compare to x86 servers - they claim "4x the density and 50% less power while delivering comparable-to-better overall performance."
Server market is still open for grab. The game here is not only the power effeciency but the space, speed and availablity is also important. ARM must know all these and so does Intel. After loosing out in personal computing space it will be interesting to see how things work out in clouds.
In response to srange, Intel competes aggressively on multiple fronts; employment, skill sets, research, applied science, investment, development, platform specification, product definition, production, supply, channel and market relations to name a few of those areas.
For leadership Intel is well known encompassing efforts at every lateral of the industrial development, compliment, channel and market system doing so like no other enterprise this analyst is aware in electronics and computing. The extent Intel's new executive team is committed to error correcting years of gaming that system, however, is yet determined. On system modifications in progress to sense, register, comprehend the need for positive change, by a legitimate management team, committed to best practice including network clean up in progress. Where two way communications for dialogue that is a constructive collaboration, are key in the success of this inter nation mission.
Presently the enterprise that is Intel is undergoing some of the most prolific changes that are many forms of reconfiguration since introduction of Tanner or the P4 to Core product transition. In this regard Intel is searching for something to sell. Whether or not Intel will succeed in identifying what channels and the market demand, over long run, at traditional Intel margins is yet to be determined. Although is continuing to successfully trade its own economic profit potential's with compliment development and channel sales for sustained support. Perhaps at levels not seen since the 1990s which can be one cause for concern?
Areas in which Intel legitimately can claim best practice are sometimes relied upon, by some in that enterprise, to deter and play down, often using invented realities that when mass communicated cloak areas in which Intel requires improvements. In an enterprise that prides itself on constant improvement propaganda and invented realities meant to misrepresent should play no role.
Two of those areas now seeming to be addressed are production and supply. Relying on the economic determinants of a total revenue total cost model to calculate Intel marginal cost, from 1993 through now, 28.6% of Intel unit volume is priced below some measure of cost; average total, variable, fixed, marginal. As an enterprise that holds channels on the weight of supply, including microprocessor stocks charged with sales incentives, Intel has been known to use production values charged with incentives to limit the ability of competitors to participate in industrial developments, too enter channels of development and channels of mass market distribution. In other words, from time to time traditionally associated with end of run, Intel production burps some amount of supply into channels that is priced economically below measures of cost. Celeron is the traditional production category example that has limited competitors in this way; on dumping. Although other microprocessor product categories are not immune from this practice over the history of 125 Intel microprocessor production run examples.
For SandyBridge product generation that economic burp is 76,744,510 units, or 19% of total SandyBridge unit volume through the production run. This subset of total supply is for the most part, quantities of product priced below cost during first quarter production. When Intel is still recovering development expense and prior too maximizing production for lowest marginal cost and highest marginal revenue. In years past, and again recently, Intel would hold off the sale of parts priced below their marginal cost until marginal cost on volume of supply, or production learning curve, had fallen below price for a marginal revenue gain. The practice was instrumental through frequency scaling and Haswell dual mobile is that most recent example on learning curve.
SandyBridge is academically of interest on the flood of 32 nanometer production prior too Intel skipping two lithography nodes ahead. Intel rarely takes risk in the availability of supplies. On unknowns of 3D transistors moving from the 32 nanometer commercial industrial art into a < 22 nm applied science, SandyBridge volumes were certainly an insurance policy on the unknowns of supplying a new lithography of product on time, in volume, at an attractive cost price ratio sustaining Intel and channel margins.
For Ivy and Haswell generation, not including all of Xeon Ivy refresh, Intel improves by the model. Which is a profit maximized production metric determined on Intel price and volume. The model is relied on by some in the investment community, and industry, for determining Intel revenue and margin into future time, for procurement negotiating Intel sales package price around weighed average for the run, and for identifying competitive product welfare space. That is where there might be free zones in Intel product and price structure to supply a competitive component.
On production metric Intel only burps 35,917,405 units of Ivy and Haswell desktop plus mobile and E5 26xx v2 priced below cost. Again these units are mostly associated with first quarter sales before reaching a profit maximized production peak. For a production model that must know Intel annual volume envelope and category splits to work, Intel is on track to lessen desktop, workstation, server, notebook mobile production priced below measures of cost.
For Ivy Bridge Haswell combined production volume that is 16% less than SandyBridge, excluding 46xx and E7 v2s. Intel improvement relieving quantities of product priced less than in quarter marginal cost is currently 8% better than SandyBridge full run. So either Intel is improving, the modeler is improving, or both. On no Haswell Core 3 production priced less than variable cost, Intel seems committed to lessening below cost production.
One indicator is a political power shift in the enterprise from Santa Clara to Hillsborough. The Oregonians no longer appear complacent to subsidize the cost of desktop and mobile.
Economic model here described was first promoted among Intel constituents, in 1997, so has a long history of use and all the likely improvements. Noteworthy 8% improvement relieving Ivy and Haswell volumes from product priced below measures of cost does not take into account the Atom product lines currently. On this partial result Intel appears to increase top of line production efficiency with the question of bottom line efficiency to be determined. Where as mainstream Intel categories seem too benefit from improvement in their cost : price ratio on product cost decreasing faster than component pricing. Which in two related examples that are Haswell ultra book and dual mobile, have seen combined i5 & i3 dual mobile price increase of 25%, on cost reduction of 32% verse Ivy dual mobiles.
Finally addressing Intel Inside which is positioned as a cooperative advertising expense cost to the microprocessor sales price, yet in system structure and channel mechanics has always been an incentive by Intel networked to lead channels toward exclusive dealing and other tying sales arrangements.
Exclusive dealing in vertical channel sales system shows intent to monopolize which is a Sherman Act Section 2 violation. Since Intel Inside was conceived, in 1991 as the tactics of a branding campaign, Intel Inside has undergone multiple system structural evolutions. Intel Inside in its original 3 Step rebated fee from is a cost taken from computer suppliers as a microprocessor purchase credit that is kicked back, by Intel, to media sales agents for registered metering of Intel microprocessors discharged through a horizontal by vertical cartel tied sales system. Two horizontal laterals of the distribution channel create a bridge monopoly that consists of computer suppliers at channel entry points and media agents at channel exit points including engaged in diminutive forms of cartel known as gyoaki and meizaru kieretsu.
As a per se price fix tie this form of Intel Inside was notoriously destructive in terms of limiting competitive potentials. It also lured criminal elements into the supply system to steal financially from the Entity that is Intel Corporation and too implement Intel product routing that artificially accelerates Intel microprocessor sales by restraining competitive sales.
Distribution channel theft from Entity Intel on confidence placement into enterprise for administering the system is minimally $13,341,000,000 that is misrepresented in the Intel financial. Distribution channel rig occurs continuously 1994 through the collapse of the dealing cartel's media agent exit points in 2008. The cost of administering tied charge back registered metering of Intel microprocessor stocks through channels is minimally on Intel financial .0203% of $517,397,000,000 revenue. Minimally on average because there is a range, Intel assesses a $4.50 charge onto microprocessors including those routed in a computer chassis. Route fees are paid by processor and computer end buyers as a channel toll way charge. Noteworthy that $4.50 only represents ½ of the Intel Inside cost burden.
Since 2008 Intel Inside has morphed into a 2 step system lacking the Intel to Computer Supplier price fix tie and Intel too media agent sales kick back. Although continues sales incentive's that encourage channel agency and exclusive dealing supporting a monopoly market share holder exceeding 80% by industry research firms IDC and IC Insights.
Intel Inside system mechanics in the 2 Step structure no longer credits a rebate from PC suppliers on the weight of microprocessor purchases for reserve by Intel for kick back to media sales agents. Instead the 2 Step system results in an added cost burden onto Intel offset in component price passed through supply system for benefit of channel members again paid by computer end buyers. Intel historically disagrees that consumer's pay cost add in processor price which is a false certification by accounting standard on the Intel financial.
Benefit of this added cost is still received by the distribution channel to offset marketing and advertising expense in support of a monopoly market share holder. Still encourages microprocessor purchase from Intel not on the merit of the product but on the merit of a sales reward for dealership. Known as a fidelity rebate of sales loyalty reward, European Union Competition Commission, 2009, determined Intel Inside as 'avoidable' cost of the processor sale. Under domestic antitrust terminology both forms of Intel Inside, 3 Step and 2 Step, are both extra economic and nonsense cost. Extra economic placing cost-add onto processor price that is a system accelerator for Intel microprocessors sales routed in channel and computer chassis. Consider the effect of 2,952,308,502 individual processor redemption coupons, averaging $4.50 each, presented to channels and what some will do to compete for securing the majority of vouchers for payment redemption from Intel.
The cost-add is a nonsense cost for four reasons. First, on the performance characteristic and design superiority achieved across most Intel processor offerings sans some of the experiments and disabled recoveries. Second, price fix tie or sales reward only benefits channels at a cost to consumers. Third, on the consistent performance of Intel designs the channel incentives were never required to convince a consumer to purchase any Intel x86 based computer. Fourth, that no more or less Intel processors would have been demanded by consumers as a result of the price fix tie and rewards for dealing that are cost to them. Price fix ties and sales rewards only encourage channels to purchase greater volumes of Intel processors
Through SandyBridge, IvyBridge and Haswell, Intel has expended $3,641,000,000 on a nonsense cost that is Intel Inside, having no consumer or society value that steals from investment, investors, research and development. As far as the branding campaign that is Intel Inside this analyst has no qualms but not at the stockholders, industries, competitors, consumers or societies continued expense.
To the extent Intel Inside is nonsense cost deterring innovation with monopoly incentive for channel sales push, Intel Inside as financial lure should be immediately discontinued.
Sources are cited here and this analyst keeps up with Intel on multiple fronts to encourage correction and remedies validating best practice, improvement, legitimate management of the Entity that is Intel Corporation.
Intel has definitely been very aggressive with its Intel Inside campaign. Its still debatable as to whether the investment they have made has been worth it, but I have seen the company expand its acquisitions and in-house research quite a bit over the years so there's little to suggest that an aggressive marketing push is distracting the company or diluting its resources thus far.