2014 will just me more of the same on the hardware side. What I hope to see in 2014 is the launch of algorithmic-based FPGA tools that can quickly create large designs using IP, processors, flexible assignment of algorithmic co-processors in fabric with software oriented code libraries for ARM processors. Let's get out of RTL and slightly better "C" code and make some real productivity breakthroughs.
Correct by construction designs that solve tedious testbench development is another wish for 2014. Anyone ready with a solution?
@DrFPGA: There is so much attitude either pro or con toward IP, vendor lock-in, registering, pipelining, etc in the FPGA community that if such tools existed no one would notice.
I believe that the OOP classes can be used to represent Verilog modules for modeling FPGAs and that get/set accessors on objects can model the interconnect to tie them together. Algorithms can be parsed to create simple micro-code for controls, and block memories can be usedfor control and operand storage.
Very little combinational logic or FFs is needed because the addresses are registered in the memories to provide the registering function.
Basically the design task is to create new memory content for functions.
Practically any HLL source code can be parsed to extract the loops, if/else, and switch/case type statements. The FPGA design can be parameterized and scaled so resources do not have to be shared and all of the RTOS kind of problems either go away or are minimized.
I am posting this to show that there will be no interest in trying new ideas.
If you are seeking an algorithm-oriented tool for FPGA design, versus RTL or block-level design assembly, go to a higher level of abstraction with ESL. We have a proven solution at Space Codesign, called SpaceStudio, which can act as a design creation front-end to Xilinx's Vivado tool suite, following a true hardware/software co-design methodology (i.e., not co-development). And we should be able to do the same for Altera, with our current API. SpaceStudio is one of the few tools in ESL that can go from algorithm (behavioral validation) to architecture (design exploration) to implementation (map to FPGA libraries, third party/legacy IP, or send C code to HLS). We published an article on this site recently ...
The acquisition of Enpirion is no small feat in what has otherwise been a tough year for Altera. FPGAs require lower voltages, lower power and they have accomplished what they sought out to do by acuqiring new IP. Although FPGAs aren't realluy involved in any way in the smartphone boom, emerging markets and the Internet of Things around them could be an important play making acquisitions such as Enpirion all the more valuable.
FPGAs will be more accepted in Automotive Market, good for Altera. FPGAs are not much accepted handsets due to the large volume and competitiveness in terms of cost and affordability, but the Automotive market is more suitable for FPGAs as the requirements and demand are totally different, this will be really helping FPGA manufactures.
OK. The IBM-GlobalFoundries and more are pursuing SOITEC SOI wafers which is very competitive for very small technology nodes. Not only power consumption is drastically reduced but as it uses way more planar structure of CMOS transistors than Intel's Fin-Fets.
The SOI yields are way better and process control easier. This will compete with way more expensive and much harder to manufacture (and test and achieve yields) 3-D. The test promblems in 3-D are according to best IEEE test standards experts close to un-surmountable. They need to be non-contact probing as otherwise minute vias will be easily destroyed during probing. That is more than a very big feat to solve. Silicon photonics is not usefull here. New approaches at Oracle may shine some light.
Also for ultra low power chips for server farms (especially for cloud) design of practically wafer-wide array of power processors is underway. They are connected by ultra low los photonic waveguides on wafer and that is compatible with SOI approach as well. This is a reuse of a standard CMOS technology and test will be with non-contact methods from wafer backside as well thus reducing any of tremendous headakes of mechanical MEMS probing. When tat is ready 3-D will slow down.
And Xilinx was 1.5 years with 2.5 D ahead of Altera. Altera is very good company but ARM is at the very core little far from FPGA approach. There is not so much of freedom in design to fit ARM tricks in FPGA as it is in ASICs (all those tricks are similar in any super-low power ARM type software. ARM is ages ahead in these against anybody). Smart-phone apps and ultra low power server farms MPUs for cloud will always be ASICs. Besides smartphones will be Altera is very good company. I would talk little more right to Altera main strengh points than their CEO did. Cheers for everybody here on Christmas Day.