NEW YORK — Rumors regarding Intel's Knight's Landing high-performance compute solution are swirling, based on leaked presentations and specifications that indicate high memory bandwidth and on-die capacity. The 14 nm Silvermont-based processor is expected to ship in 2015.
Knight's Landing is a 14 nm process node, compared with Intel’s 22 nm Knight's Corner, Haswell, and Ivy Bridge server processors. It will, according to leaked specifications, include a 1.4 GHz base frequency, 300 W thermal design power, and 72 cores. Its DP FLOP/core is 32 FLOP/cycle and its DP GFLOP/core is 44.8 GFLOP/s. The raw FLOP/s improvement is greater than 2.5x.
Clearly, Intel is making a significant investment in this chip. It is a clear sign that Intel sees HPC as critical to its continued success in the server market in general. Although Nvidia is doing quite well in the HPC market with its high-powered offerings, Intel is keeping things quite competitive.
It would appear that the significant gains in performance compared with Knight’s Corner are not completely accounted for by the shift to a 14 nm process node. Knight’s Corner fell short in several ways. Unlike Knight’s Corner, Knight’s Landing makes use of Intel’s investments in eDRAM and Skylake among other crucial resources. Intel is also taking its time, this time, in bringing its latest HPC solution to market -- unlike with Knight’s Corner.
Knight’s Landing’s estimate diverges slightly from the specifications that have been rumored as it comes with 512 kB of shared L2 cache, rather than 1 MB. Cache read bandwidth and large shared L3 cache are also to be expected, as the L3 cache is predicted to be about eight times the size of the L2 caches, up to 144 MB.
Most significantly, the memory hierarchy and cache bandwidth has increased by an even greater factor than in previous Intel HPC offerings. The on-die capacity has increased, apparently, by almost a factor of 5. Expect much greater single-threaded performance as well, while Intel moves to the Silvermont, which enables a greater number of workloads to stay within the Knight’s Landing platform. It is even a possibility that the system’s x86 core could turbo to much greater frequencies during the time that the vector units are dormant, achieving even better single-threaded performance on scalar, latency-sensitive code.
What’s lost as a result is space on the silicon die. As of right now, according to David Kanter's article on the website Real World Technology, Intel’s biggest chip is codenamed Tukwila and measures 700 mm2. Knight’s Landing may actually surpass Tukwila in volume. In addition, according to Kanter, data arrays for 1 GB of eDRAM by themselves account for 1,000 mm2. If one adds to that the control logic and i/Os, the size is likely to increase to 1,200 mm2, spread out across a number of chips.
Intel is going to keep Knight’s Landing under wraps until one of two events later this year -- either Hot Chips or SuperComputing -- according to David Kanter's article. Until then, a combination of informed rumor and wild surmise will have to suffice, as only a few select customers will be privy to the actual details.
— Zewde Yeraswork, Associate Editor, EE Times