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Slashing Costs in 3D IC Wafer Process

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vacuum-dependent bonding?
resistion   1/28/2014 2:59:28 PM
If the bonded wafer needs to go into a vacuum for further processing, it could slip off, right?

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Progress in 3-d chip stacking has been held back by..
chipmonk0   1/27/2014 11:56:51 AM
too many Govt. funded European Labs getting involved and putting out misleading white noise branded as scientific research. They are neither result oriented nor sufficiently grounded in Physics or comprehensive methodologies to develop whole new technologies for commercial application. Rather than comprehend the total challenge they indulge only in piecewise optimization - the result : endless "Technical" Conferences that evade the core technical challenges but keep harping on cost & supply chain issues instead!

Only belatedly have these European "Researchers" recognized the folly of the process flow ( derived from "Powerpoint Engr." w/o the benefit of Physics, data or even Engr. common sense ! ) they have been blindly following and so now this article talks about the issues related to temporary bonding / debonding steps in 3-d stacking of wafers / dice !

The whole wafer bonding / debonding step that these European Labs & Suppliers are still going on about has been eliminated by US companies who are now making 3-d stacked chip products commercially with a radically different material set & process flow.



zewde yeraswork
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zewde yeraswork   1/27/2014 11:43:31 AM
It may be necessary to strike a balance between high costs on the one hand and other limitations on the other hand.

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