At Grenoble’s 3D TSV Summit, which took place this week on Minatech’s campus, the talks were about 3D IC manufacturability, and all its associated costs, or how to trim them to make 3D IC packaging a cost-effective winner for most markets, not just niche applications.
IC design aside, there are many processes involved before dies can be stacked together, including the manufacture of Through Silicon Vias (TSVs), wafer handling and thinning, TSV reveal etching, and Chemical Mechanical Planarization (CMP), then applying micro-bumps to finally stack another wafer or selected know-good dies.
Of course, one way to reduce materials’ costs in these IC-stacking processes is to avoid excess material in the first place and etch minimal layers to reduce the subsequent CMP step (and associated chemical costs).
Wafer handling is a costly issue, especially when the wafer is going to be so thin (down to 50µm for the current state-of-the art) that it behaves like a foil and must be securely bonded to a carrier in order to go from one process equipment to the next.
Currently, the norm is to use temporary adhesives, with their own set of issues. They require specific temperature and chemical resistance, yet the adhesives should be removed easily for de-bonding, without leaving a trace. This not only makes these special, temporary bonding adhesives costly and their use a yield-issue, but the dedicated machines that dispense, cure, then de-bond and remove the remaining adhesive add their contribution to the multimillion-dollar capital expenditure necessary for 3D IC manufacturing.
The story continues on EE Times Europe.
— Julien Happich writes for EE Times Europe. EE Times Europe