SANTA CLARA, Calif. — New kinds of memory interfaces, memory chips, and processors are coming that will offer more performance and new capabilities for engineers who adopt them, Thomas Pawlowski said in a keynote at DesignCon. "Embrace the change. Don't resist it."
The chief technologist at Micron Technology sketched out the general trend toward abstracted memory interfaces and new kinds of memory chips. He gave a more detailed description of a promising processor architecture that Micron has in development. The Hybrid Memory Cube (shown below) "shows the shape of things to come" in abstracted memory interfaces. HMC is a dense stack of memory die in a package that breaks through memory-bandwidth limits with an interface that delivers 160 Gbyte/s.
The HMC interface "exposes nothing -- just a SerDes interface with a simple command set. All the details are not your problem." Such highly optimized interfaces built into DRAMs are the wave of the future. They will replace lowest-common-denominator standards hammered out between processor and memory vendors in committees that "left performance on the table for decades."
In an interview after the keynote, Pawlowski said the Jedec standards group has "nothing in the pipeline" after its DDR4 high-end DRAM interface. However it is developing a family of low-power DDR interfaces, as well as Wide I/O, an interface for attaching a memory chip directly to a processor.
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