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Slideshow: DesignCon Hits 100G Targets

2/3/2014 00:02 AM EST
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Ed Connolly
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PCB material
Ed Connolly   2/3/2014 6:06:45 PM
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What is the laminate?

krisi
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CEO
Re: 56G serdes? 802.3bj panel?
krisi   2/3/2014 5:46:52 PM
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so what is the highest IO bandwidth per pin in all these solutions? 100G in parallel was demonstrated in R&D several years ago (you just need enough pins to carry 100G in aggregate)

rick merritt
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56G serdes? 802.3bj panel?
rick merritt   2/3/2014 3:07:33 PM
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I did NOT get to the LSI session om 56G serdes or the panel on 802.3bj 100GbE backplanes.

I'd love to hear a report from anyone who did!

Susan Rambo
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Oscilloscope watch teardown!
Susan Rambo   2/3/2014 12:42:47 PM
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Wow, I missed the Oscilloscope watch teardown at the show. Good slideshow. I think you hit some important stuff at the show. Martin Rowe might want to chime in about some developments in PCI-Express he saw from the show.

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