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Slideshow: DesignCon Hits 100G Targets

2/3/2014 00:02 AM EST
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Susan Rambo
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Oscilloscope watch teardown!
Susan Rambo   2/3/2014 12:42:47 PM
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Wow, I missed the Oscilloscope watch teardown at the show. Good slideshow. I think you hit some important stuff at the show. Martin Rowe might want to chime in about some developments in PCI-Express he saw from the show.

rick merritt
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56G serdes? 802.3bj panel?
rick merritt   2/3/2014 3:07:33 PM
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I did NOT get to the LSI session om 56G serdes or the panel on 802.3bj 100GbE backplanes.

I'd love to hear a report from anyone who did!

krisi
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Re: 56G serdes? 802.3bj panel?
krisi   2/3/2014 5:46:52 PM
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so what is the highest IO bandwidth per pin in all these solutions? 100G in parallel was demonstrated in R&D several years ago (you just need enough pins to carry 100G in aggregate)

Ed Connolly
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PCB material
Ed Connolly   2/3/2014 6:06:45 PM
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What is the laminate?

rick merritt
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Re: 56G serdes? 802.3bj panel?
rick merritt   2/4/2014 2:54:50 AM
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@Kris: A good question: what was the highrest bandwidth per pin shown at DesignCon. A beer for whomever can answer that one!

MeasurementBlues
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Re: 56G serdes? 802.3bj panel?
MeasurementBlues   2/6/2014 10:37:06 PM
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100G Started as 1x10G and now is 2x25G. Well, 4x28G because of bit overhead. Most of the talk at DesignCon is per lane rather than aggregate. The major issue with aggregating is channel-to-channel crosstalk. Most of the issues are just simple getting 26G and 32G to run reliably, All kinds of issues come up such as insertion loss, reflections, intersymbol interference, and skew. At these speeds, differential pairs mismatched by even 1mm have skew prodlems.

MeasurementBlues
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Re: 56G serdes? 802.3bj panel?
MeasurementBlues   2/6/2014 10:39:08 PM
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I just posted an article about characterizing a 28Gb/s channel and how to de-embed the losses from the channel to get a clean measurement of the signal at the receiver.

DesignCon paper and tutorial explain de-embedding

 

krisi
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Re: 56G serdes? 802.3bj panel?
krisi   2/7/2014 10:25:44 AM
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thank you Martin...28 Gb/s it is...what kind of errror correction is used that is responsible for the extra 3 Gb/s?...Kris

MeasurementBlues
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Re: 56G serdes? 802.3bj panel?
MeasurementBlues   2/7/2014 10:36:05 AM
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@krisi, most of those data streams use 66b/64b encoding and some may use 128b/127b. There was a lot of talk about using forward error correction, particularly where these serial buses might carry data-storage protocols. For example, SATA protocols riding on PCI3 GEN 3 physical layer.

See Exercise those storage devices for more.

MeasurementBlues
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Re: 56G serdes? 802.3bj panel?
MeasurementBlues   2/7/2014 10:37:42 AM
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@krisi, does Rick Merritt owe me a beer?

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