Sonics' Brinks describes the hardware IP-based power management approach as "unique." He says, "I didn't come across anything like it, in all of my research" before filing a patent for the new IP back in August, 2010.
Intelligent Power Controller takes advantage of "an unfair advantage" Sonics has created since the company developed on-chip network technologies, Brinks says.
Since its inception in 1996, Sonics has developed a broad portfolio of interconnect IPs to help SoC designers. The company's system IP transforms unrelated components -- often speaking different languages -- into holistic systems that communicate better and work better.
In developing the Intelligent Power Controller, Sonics engineers have tightly coupled the new hardware-based power management IP with Sonics' existing interconnects, to tie in "on-chip network" fabrics.
The Intelligent Power Controller defines and supports an advanced communication protocol between the power controller and functional blocks -- including status, state and activity, and commands.
The Controller extends power management to all system components inside SoCs. By taking a methodology that goes beyond the CPU-centric approach, Sonics' power management encompasses software, master, slave, and interconnect. Its goal is to provide a set of coherent power management policies across the system. The hardware also handles transitions between states. It is reactive, and is data-flow driven, the company says.
Clearly, Sonics' new hardware IP is designed to "work a lot better" with its own on-chip network's fabric, says Brinks. But it can also work independently.
The new hardware IP does not sit in a traditional power management IC (PMIC) but in the main SoC. At a time when board-level power management functions are moving to an SoC, actual "thinking" on power distribution between CPU and cores belongs to the SoC. The PMIC, meanwhile, is responsible for doing the actual power shutdown.
So, has Sonics' new hardware-based power management IP proven itself in real-world applications?
Brinks noted that by taking a SystemC-model approach, Sonics' team has already characterized and verified its power management IP on an MP3 decoder platform. Meanwhile, the team is currently running the IP on an FPGA to see how it works during more complex activities.
When asked about actual power savings enabled by the hardware-based power management IP, Brinks claims "up to 50 percent power savings, depending on type of applications and the particular SoC implementation."
With the new hardware IP, Sonics is promising SoC developers will "significantly reduce power consumption by shortening power transition times and eliminating associated CPU overhead" and "automatically instantiate and verify distributed power management hardware."
Asked how big the hardware-based power management IP is, Brinks says its geometry is "tiny," and its gate count is in tens of thousands to 100,000 gates. The core, which includes a small CPU like ARM 7, is designed to touch all corners of a die on a SoC's on-chip network.
Brinks says Sonics is currently making the new hardware IP available to two or three lead customers. "By closely working with our lead customers, we hope to find if there's anything that we may have missed."
The same IP is slated for general distribution later this year, he notes.
Asked if Sonics plans to license the new power management IP to ARM, Brinks says it depends on negotiations, and "if ARM is coming to us" and asking for it.
Last May, Sonics announced that ARM has acquired a license to the Sonics patent portfolio. Sonics also said at that time that the two companies would cooperate to support Sonics' power management technologies.
— Junko Yoshida, Chief International Correspondent, EE Times