SAN JOSE, Calif. — In separate talks, Intel and TSMC revealed two new efforts that are rekindling hopes for extreme ultraviolet lithography. EUV has long been seen as one of the most promising tools to ease the mounting complexity of making a future generation of smaller, faster chips.
Intel and TSMC want to use the ultra-fine patterning systems to make their generation of 7 and 10 nanometer chips starting in about 2017. But such aspirations have been dashed many times: EUV was originally targeted at use as early as 2007.
Making chips is "becoming a game of accounting for every nanometer, and that's not possible without a rigorous and mathematically sound approach," said Mark C. Phillips, head lithography engineer for Intel, in an interview with EE Times.
At the SPIE Lithography conference here, Phillips disclosed a new analysis tool under development at ASML for handling edge placement errors in next-generation chips, a growing problem with multiple causes. Just one aspect of the new modeling tool "takes about 10 pages of math to explain," said Phillips who asked ASML to start working on the concept after a meeting last year.
The new modeling tool could be key for so-called complementary lithography, a hybrid approach using existing immersion systems for some jobs and new EUV systems for others, Phillips told us (see chart below). The approach requires using increasingly strict design rules and putting wafers through litho systems multiple times.
"There's a lot of discussion about the industry moving in that direction -- we started working on it earlier than most so we have more experience in it," he said.
In 2012, Intel committed to invest about 4 billion dollars in ASML, the developer of EUV, to help drive the work forward. Later that year TSMC pledged to invest a billion dollars in ASML, too.
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