Cadence has just announced a new TimingVision technology within the Allegro PCB Designer solution that is mind-bogglingly clever and that can speed the timing closure of high-speed PCB interfaces -- such as a DDR3 memory interface -- by 60% or more. To put this another way, you can lock down your interfaces in a third of the time, which is huge!
I remember back in the mid-1980s working with one of the early PCB layout tools. This was a humongous, dedicated system -- hardware and software -- that involved two massive (for the time) monitors, a keyboard, and a digitizing tablet. One of the monitors was black and white (color was really expensive); this was used for command-line input. The other monitor was color; this was used to display the tracks and vias and suchlike.
The only thing this incredibly expensive system did was lay out circuit boards. And when I say "it laid out boards," I'm being somewhat sparing with the truth. It was the operator that laid out the board, placing the vias by hand and then placing individual track segments. There were no automatic routing capabilities, no drag-and-drop, no plow functions. (We did have pan and zoom, but they were so slow that you could go and get a cup of coffee while they took place.)
Of course, the whole board design problem was much simpler in those days. Clock speeds were lower and the various interfaces were much simpler. Today's designs, by comparison, involve eye-wateringly high clock frequencies coupled with incredibly sophisticated standards-based interfaces, including DDR2, DDR3, and DDR4, and PCIe Gen1, Gen2, and Gen3. On top of all of this, supply voltages continue to be reduced, from 1.8V to 1.5V to 1.2V, all of which makes signals increasingly sensitive to crosstalk effects and ripples in the power supply.
The end result is that circuit board designers are presented with a mind-bogglingly complex set of electrical and layout implementation constraints. Existing tools present a lot of challenges with regard to achieving timing closure, not the least that interdependencies and margins between groups of signals have to be hand-calculated by the designer. Also, timing closure is an iterative process; PCB designers end up bouncing back and forth between the design and the constraints manager; you fix one lane, then you fix another, then you have to return to "re-tweak" the first one; and so it goes.
Cadence's new TimingVision technology addresses all of these issues. The sophisticated timing engine embedded in the Allegro PCB Designer solution analyzes signal interdependencies to develop delay and phase targets, and it helps designers to develop their strategies to address timing issues. Real-time visual feedback on the design canvas presents color-coded timing and phase information; e.g., green is good, red is short, and yellow is long (the colors can be user-modified to accommodate those with color vision issues).
Coupling the TimingVision analysis with auto-interactive technologies -- Auto-interactive Delay Tuning (AiDT) and Auto-interactive Phase Tuning (AiPT) -- significantly reduces time and effort on the part of the designer. Consider the following illustration, for example, which shows Allegro TimingVision guiding the auto-interactive delay-tuning:
Allegro TimingVision guiding AiDT
(Click here to see a larger image.)
To be honest, I find it difficult to wrap my brain around how complex everything is with regard to the design problem itself. It's no longer sufficient to ensure that the two signals forming a differential pair are of the same length -- you also have to ensure that the phase of the signals is constrained within very tight tolerances. For example, consider the following illustration, which shows Allegro TimingVision guiding the auto-interactive phase-tuning:
Allegro TimingVision guiding AiPT
(Click here to see a larger image.)
The thing about existing tools is that they are often clever enough to tell you that something is wrong, but they aren’t clever enough to focus your attention on the particular area of interest. As illustrated in the image below, a DRC tool might indicate that the entire net is not meeting a +/-10mil static phase rule, for example.
By comparison, as illustrated in the image below, Allegro TimingVision can isolate the problem and indicate which "rat" of the net needs to be modified in order to meet the desired constraint.
But wait, there's more, because Allegro Sigrity users can combine TimingVision with Sigrity power-aware signal integrity (SI) analysis to rapidly implement and accurately assure compliance with memory interface specifications. The combination of all these technologies enables product creation from IP to SoC to package to PCB to system -- all predictably and cost-effectively (click here for more information).
Do you remember ye olden times? Did you work with the old layout tools? Can you imagine going back in time with a modern workstation loaded with these tools and showing them to everyone? And can you imagine working on today's high-end PCBs without modern technology to help and guide you?
— Max Maxfield, Editor of All Things Fun & Interesting