I just got off the phone with Steve Glaser, senior vice president of corporate strategy and marketing for Xilinx. He very kindly brought me up to date on his company's forthcoming UltraScale MPSoC devices, which will be introduced at the 16nm technology node.
Actually, this can all be a tad confusing, so let's take a moment to set the scene. When Xilinx adopted the 28nm technology node, it released its lowest-power, smallest-form-factor Artix; its best price-and-performance per watt Kintex; and its high-capacity, high-bandwidth Virtex families at this node. It also released its Zynq All Programmable SoC devices at the 28nm node.
The current All Programmable SoC at the 28nm technology node, the Zynq, is hardware, software, and I/O programmable. It boasts a homogenous dual-core ARM Cortex-A9 microcontroller subsystem (running at up to 1 GHz and including floating-point engines, on-chip cache, counters, timers, etc.), coupled with a wide range of hard-core interface functions (SPI, I2C, CAN, etc.) and a hard core dynamic memory controller. All this is augmented by a large quantity of traditional programmable fabric and a substantial number of general-purpose input/output pins.
When we come to the 20nm technology node, only the Kintex and Virtex families are being brought forward with the UltraScale architecture. The Artix family will hold the fort at the 28nm node. When we say UltraScale, we're talking about a radical new FPGA architecture that offers massive -- ASIC-class -- I/O bandwidth, memory bandwidth, and DSP processing capabilities. In the case of the programmable fabric, we're talking about millions of logic cells all supported by ASIC-class data-flow and routing resources.
The first 20nm UltraScale devices started shipping in December, but Xilinx is already looking to the 16nm future. In addition to UltraScale FPGAs and 3D ICs, the company will field a family of 16nm multi-processor SoCs (MPSoCs). In addition to UltraScale FPGA fabric, these devices will boast a heterogeneous multicore processing capability.
The software-programmable portion of this image shows and ARM processing element augmented with real-time, graphics, video, waveform, and packet processing units. Xilinx isn't releasing too many details at this time. In particular, it is being very cagey about the identity of the ARM core(s). It will say these devices will offer a combination of new and next-generation processing and programmable engines optimized for different application tasks. Also, the devices will be scalable from 32 to 64 bits with support for virtualization. This scalability includes CPU, interconnect, peripherals, processing engines, and an address space measured in terabytes.
My understanding is that different members of the family will be targeted toward different applications, as illustrated below.
Of course, I cannot contain my excitement to know exactly which ARM processor Xilinx will announce. Will it be a dual or quad core -- or even more? What do you think?
— Max Maxfield, Editor of All Things Fun & Interesting