TSMC’s 16nm FinFet technology is making its way out in to the world to offer even more transistors to use. The ramifications for FinFet, as well as several other issues related to chip design, are just of the subjects that are expected to be discussed and debated at the CDNLive conference, which starts March 11 at the Santa Clara Convention Center in Santa Clara, Calif.
In his talk, Bob Mullen, technical manager for Design Methodology and Design Technology Platform for TSMC, is expected to detail information about the custom design reference flow and all the elements that make this a front-to-back flow. At the same time, another FinFet user, Intel, is tackling the complexities of designing at this node.
Laurent Isenegger, a senior system modelling engineer at Intel, is showing how linking his company’s CoFLuent Studio software with Cadence’s C-to-Silicon tool works across multiple consistent hierarchies to speed development with a high-level design approach. Low power is also another key theme that is increasingly important in a high-level design methodology with the latest process technologies.
Mark Warren a field group director at Cadence is looking at how high-level synthesis can help reduce power, while Leah Clark, an associate technical director at Broadcom, is looking at how CLP helps deliver full chip static power verification for the chips that will be using these leading-edge process technologies.
ARM’s Raviraj Mahatme is also looking at the innovations in low power design for the Cortex-A53 processor, the “little” core in a big.LITTLE implementation. Other keynote speakers for the conference include Lip-Bu Tan, president and CEO at Cadence; Krishna Yarlagadda, US president of MIPS CPU core developer and the POwerVR graphics developer for ImaginationTechnologies; and Chris Rowen, founder of Tensilica and now a Cadence Fellow.
In addition, Cisco Systems, Hewlett Packard, Samsung Microchip, and Freescale Semiconductor will have engineers on site to talk about the challenges facing their chip designs, as well as the issues of board and package design.