SANTA CLARA, Calif. — Low-power, security, cloud, and IoT were the looming themes in Cadence CEO Lip-Bu Tan’s keynote at CDNLive, Cadence Design Systems’ user conference for IC designers on Tuesday, March 11. Cadence was selling an expanded view of what systems design means on the ecosystem level: From IC and IP to SoC and PCB, it's all part of an enlarging ecosystem.
Over the past year, Cadence has been on an IP acquisition spree, which included Tensilica, Forte Design Systems, and TranSwitch. But as EE Times reported in 2013, Cadence’s competition had also started amassing IP.
Reminding the audience frequently of his background as a venture capitalist, Tan made a point to say he attended Mobile World Congress and CES to check out end products. Understanding the final consumer products is part of the system-wide approach.
Cadence had four ARM-related announcements at CDN-Live, including ARM Fast models added to Palladium II and the test chip with ARM-Cortez-A12 in 28nm-SLP process. Cadence’s physical verification system was also certified for GlobalFoundries' 65nm to 14nm FinFET processes.
President & CEO, Cadence
(Source: EE Times)
During the Keynote, Lip-Bu Tan was joined on stage by Krishna Yarlagadda, president of Imagination, and by Cadence Fellow Chris Rowens, from Tensilica.
The Holy Grail is cutting cost, power, and development time. “Pretty much everything is going to be connected,” said Yarlagadda during the keynote. “Ten years from now, you can’t imagine any processor without connectivity.”
Later, in a semi-fireside chat with press, he cautioned that the hardware and software has to be simplified to keep the cost down to achieve nirvana of "everything is connectedness."
“IoT will happen,” Yarlagadda said, but right now we have only parts of the full package. “We can make a demo happen but don’t have wearables that are marketable...” in other words, they are not power efficient and cost too much.
As a point of pride, Yarlagadda said, “Frankly, our industry, EDA has fueled this process.”
President, Imagination Inc.,
during press meeting at CDNLive.
(Source: EE Times/Susan Rambo)
Although the people getting the fruits of this are higher up in the industry, EDA is probably the most complex software out there, he said, noting that it was a good time to be in IP and SoC design: It’s the hard stuff, but someone has got to do it.
Chris Rowen used the analogy of the power-of-10 theme during the keynote to explain challenges at different points in the design process and in different systems levels from the macro to the micro and below. He was eloquent about engineers knowing when they should design power savings into the hardware -- the SoC design -- and when to use software to get the savings. He believes an engineer can know what to do based on the situation if there were guides to follow. “We need an energy-informed algorithm design.”
Rowen, at a press lunch, said Tensilica’s integration with Cadence went well, with the Tensilica team moving en masse to Cadence’s offices. "It was good to have the whole team intact," said Rowen.
— Susan Rambo, Executive Editor, EE Times
Article updated 3/14/14