TORONTO, Canada -- As DDR4 awaits widespread adoption and new technologies such as hybrid memory cube continue to be fleshed out, there remains opportunity to improve on DDR3’s performance, and more importantly, its design and manufacturing.
Last week, Samsung announced it was mass producing what the company said is the most advanced 4Gb DDR3 memory based on a new 20 nanometer process technology using immersion ArF lithography.
Sylvie Kadivar, senior director for strategic DRAM marketing at Samsung Semiconductor, said the advancement overcomes the DRAM scaling hurdle, which she said is more difficult than scaling with NAND flash. “This new design approach has addressed the challenge of scaling, which the design community has been facing as they are heading into the future, such as the 10 nanometer lithography,” she said. “It’s not only important for DDR3 today, but it’s also going to be important for DDR4.” The challenge has been what is beyond 20 nanometers and what’s going to happen next, Kadivar said.
A key element of the new design and manufacturing technology is a modified double patterning and atomic layer deposition that allows for continued scaling. The new approach to double patterning enables 20nm DDR3 production using current photolithography equipment, Kadivar said. “We have found the most efficient way to manufacture high density DDR3 technology, in this case 4Gb.” Samsung has also created ultrathin dielectric layers of cell capacitors with a very high level of uniformity, which is an important contributor to higher cell performance.
Samsung defines 10nm-class as a process technology node somewhere between 10 and 20 nanometers, and 30nm-class as a process technology node somewhere between 30 and 40 nanometers. In addition to addressing the scaling challenge, Kadivar said Samsung also has improved manufacturing productivity, which is more than 30% higher than that of the preceding 25 nanometer DDR3, and more than twice that of 30nm-class DDR3.
From a performance perspective, the new 20nm 4Gb DDR3- based modules can save up to 25% of the energy consumed by equivalent modules fabricated using the previous 25 nanometer process technology. “Power is always a constraint,” said Kadivar. “Knowing you can reduce the power consumption further is a significant advantage.” Higher density components often mean higher density modules and the challenge is to make those modules as energy efficient as possible, she said.
Victor De Dios of De Dios and Associates said the modified double patterning technology is the most significant of Samsung’s new process design and manufacturing achievements. “The key is they went one more step while extending the double patterning,” he said, which minimizes the capital spending on new equipment and tools for manufacturing.
De Dios said the next step would be to move to more beyond double patterning -- triple or quadruple patterning. “That changes a lot of equations in the manufacturing process.” There has been bigger changes in process transition in the past than what Samsung has announced, he added, but since it’s becoming more difficult to achieve these milestones, moving a few percentage points is still significant.
New processes are going to be needed for new DRAM products as result of demand from mobile devices and computing applications, said De Dios. “You’re going to need more advanced processes to enable a lot of the new products.” Smartphones, PCs, and servers are dependent on the DRAM moving forward with improved process technology, he said. Once the domain of science and research, high-performance computing is also going more mainstream and placing demands on DRAM.
Shrinking geometries below 20 nanometer and producing advanced components cost effectively is an ongoing area of research. MIT researchers, for example, have developed directed self-assembly techniques that they claim resolve the issues associated with the two main lithography techniques used in the semiconductor manufacturing process today -- photolithography and electron-beam lithography. MIT’s hybrid process is based on a simplified template, in which complex patterns of line, bends, and junctions with feature sizes below 20 -nm can be made using block copolymer self-assembly.
Another area of lithography under investigation is extreme ultraviolet (EUV) lithography, and widely considered to be a work in progress.