SAN JOSE, Calif. — GlobalFoundries will describe, in May, a way to make 3D chip stacks without a large keep-out zone around its through-silicon vias. The work is being hailed as an advance in silicon integration at a time when Moore's Law is slowing getting more costly.
In a paper at the IEEE International Interconnect Technology Conference in San Jose, GlobalFoundries will describe a middle-of-line (MoL) chip stack in a 20 nm planar process, which achieves a "near-zero" keep-out zone around its TSVs. Prior work used keep-out zones measuring seven microns or larger, wasting silicon space and driving up chip costs.
Globalfoundries will use the technique in its commercial 20 nm process, said Mohamed A. Rabie, the paper's author and a member of technical staff at the company, speaking in an email exchange. He pointed to a description online of the foundry's via-middle approach.
A keep-out zone of just three microns could take up 113 square microns on a chip, four times the 28 square microns of the TSVs used in the GlobalFoundries work, says Herb Reiter, a 3D IC expert who reviewed the paper. For large graphics chips expected to use 10 thousand TSVs or more, "the area savings of a zero keep-out zone... will remain very significant," Reiter said.
In addition, "Less strain between TSVs and surrounding silicon will also improve reliability of ICs, especially in regard to maintaining good contacts between TSVs and interconnect layers."
For years, engineers have been pursuing 3D chip stacks as a way to make smaller, faster devices. They aim to create an alternative to typical CMOS process shrinks, which are becoming more complex and costly due to the lack of new lithography tools. But the 3D efforts have been dogged by a variety of technical and business issues -- including the large keep-out zones around TSVs -- that makes the approach still costly for most uses.
The MoL layer stack GlobalFoundries describes uses nitride, PMD oxide, and a contact protection layer with a high coefficient of thermal expansion. The CTE is about four times higher, and the elasticity modulus is a third lower than used in previous chemical-mechanical planarization (CMP) stop layers. Thus the stop layer will "shrink at a faster rate than the underlying silicon, resulting in high tensile strain in the CMP stop layer," according to the paper.
The stop layer will "shrink at a faster rate than the underlying silicon, resulting in high tensile strain in the CMP stop layer," reads the paper. The main challenge was finding a stop-layer material that could "balance the TSV stress but not cause additional stress in silicon that might still affect active devices negatively," says Rabie.
A cross section of GlobalFoundries' full stack with TSVs shows an oxide liner thickness of 278 nm.
Engineers have worked on similar approaches using stress-reduced annealing. Separately, Tezzaron has shown a design using tungsten that has a CTE similar to silicon and thus can eliminate the keep-out zone, Reiter notes.
GlobalFoundries did not provide cost estimates for using its annealing process, key to its overall viability in production, Reiter noted. In addition, the paper did not address how the technique would be used with FinFETs, a 3D transistor structure that GlobalFoundries, TSMC, and others will employ at 16 nm and smaller nodes, he said.
Although the current paper lists only authors from GlobalFoundries, to date the company has been working with partners on 3D IC processes. By contrast, its larger rival, TSMC, is going it alone so far with an in-house process.
In other papers at the event, researchers at CEA-LETI will describe 50nm TSVs in a 14 nm process, enabling dense chip stacks with multiple layers. Researchers at Imec will report on a fivefold improvement in carbon nanotubes as chip interconnects, approaching the performance of copper, which is widely used today.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times