In the face of potentially higher costs, "people will try to use today's 28nm node as much as they can," de Geus said. "Only a few people will move to the 20nm node [because its] benefits are not that high, so they will wait for 16/14nm nodes," he added.
That could open the door to alternatives such as the fully depleted silicon-on-insulator technology proposed by STMicroelectronics and others. "But it would take [other] major players to put their weight behind" FD-SOI for it to take off, he said.
Given the increasing costs and complexity of making chips, semiconductor companies have put off a shift from 300 to 450 mm wafers until 2020, he said. Larger wafers can sometimes provide lower costs but they also require "a complete retooling of the industry and that's not happening right now," he said.
Nevertheless, the Synopsys executive remained upbeat at the event where he launched an upgrade of the company's main chip design software. "We support multiple billion-transistor chips, and we will see a continuation of that work for the next ten years," he said.
Interestingly, only about five percent of the designs done in Synopsys' tools are at today's leading-edge 28nm process, according to one foil in de Geus's keynote. The 180nm node is the most popular, used by nearly 30% of the designs using its tools, followed by the 65nm and 250nm nodes.
"It's an amazing spread -- I had to look twice at that graph to make sure the numbers were correct," de Geus said. "We do see the bulk of the designs gradually moving up and I think that will continue, but we will see a bunching up at 28nm and then slowly an increase to the 16/14nm nodes," he said.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times