Intel's year-old foundry deal with Altera has been expanded to include "multi-die" devices that combine Altera's Stratix 10 FPGAs and SoCs with DRAM, SRAM, ASICs, processors, and analog chips in a single package.
The agreement, announced March 26, is an extension of a deal the companies announced in February 2013 when Intel said it would manufacture FPGAs for Altera using its 14 nm FinFET process technology. Incorporating interconnect packaging and semiconductor technologies from both companies, the single system-in-a-package will yield the highest levels of integration and density achieved using traditional 2.5 and 3D chip-packaging approaches but at a reduced manufacturing cost.
Using its 14 nm Tri-Gate process technology, Intel will build Altera's FPGAs, which will aim to address the performance, memory, bandwidth, and thermal issues affecting the communications, high-performance computing, broadcast, and military sectors, the companies said.
"Our partnership with Altera to manufacture next-generation FPGAs and SoCs using our 14 nm Tri-Gate process is going exceptionally well," said Sunit Rikhi, vice president and general manager, Intel Custom Foundry, in a press release. "Our close collaboration enables us to work together in many areas related to semiconductor manufacturing and packaging. Together, both companies are building off one another's expertise with the primary focus on building industry-disrupting products."
Altera, based in San Jose, Calif., has been leveraging Intel's manufacturing prowess to give its advanced FPGAs advantages in density, performance, and power over rival FPGA maker Xilinx, which partners with TSMC as its foundry. When the companies announced their partnership a year ago, Altera CEO John Daane said besides winning more business away from Xilinx, the 14 nm parts could help Altera grab more sockets away from ASICs and application-specific standard devices.
For Intel, offering foundry services helps the chipmaker lessen its dependence on the waning PC sector. In its fourth-quarter conference call with analysts, Intel CEO Brian Krzanich said that he believes Intel has "leadership position in transistor cost," and can scale transistor costs at 14 nm to drive a gap between itself and the leading foundry.
Earlier this month, Intel demonstrated a general-purpose, 14 nm SerDes chip designed to reduce the size of its previous 22 nm SerDes offering by about 40%. These new SerDes chip are also designed to cut power consumption by about 20%.