It's not often that you see something that makes you think "this is a game changer." The introduction of logic synthesis circa 1990 was one such event; today's introduction of SDNet from Xilinx may well be another.
In the not-so-distant past, network nodes were -- to a large extent -- fixed and frozen. Each of the big players, like Cisco, had its own propriety solution in which both the control plane and the data plane were largely realized in hardware using ASICs or ASSPs.
More recently, we saw a move toward what is referred to as software-defined networks (SDNs). In this case, what we are talking about is a software-defined control plane with network intelligence. However, the data plane remains frozen in hardware.
The advantages of having a software-defined control plane include flexibility, the ability to support virtual network services, and the ability to provide holistic network management. In turn, this allows datacenter and WAN operators to customize, differentiate, and improve their networks in software. However, the data plane's packet processing is so computationally intensive that it has to be performed in hardware. The problems associated with a fixed data plane include the creation of expensive ASICs (which we will take to encompass ASSPs and SoCs), limited differentiation, and costly-in-field upgrades.
Now, Xilinx is introducing the concept of "softly" defined networks. Having a software-defined data plane with content intelligence that is still implemented in hardware provides wire-speed data processing that is protocol-agnostic and complexity-agnostic. It supports per-flow, flexible services provisioning; it facilitates differentiation; and it supports in-service "hitless" updates.
"Softly" defined networks
How is all of this possible? Well, not surprisingly, it involves the use of today's state-of-the-art FPGAs, which provide hardware speed coupled with the ability to be configured to do whatever you want. But that's not the interesting part. The interesting part is how we tell the FPGAs what we want them to do. This is the real game-changing portion of the equation. Xilinx has created what it calls the Software Defined Specification Environment for Networking (SDNet) environment as illustrated below:
The system architects donít have to understand anything about the underlying FPGA devices and their internal architectures. All they have to do is define the "What" -- i.e., what they want to do. They donít concern themselves with the "How" -- i.e., how the implementation will be realized. The SDNet specification captures the required packet parsing, packet editing, packet manipulation, and packet lookup/search activities. The specification also captures required quality of service (QoS), policing, filtering, congestion management, provisioning of services, and suchlike.
The SDNet specification is then fed into the SDNet compiler, which also accesses a library of IP cores. The output from the SDNet compiler is then fed into the Vivado suite of design tools, which handle the nitty-gritty implementation details. The output from Vivado is an executable image that can be loaded into the Xilinx-FPGA-based, softly defined linecard.
Depending on what the system architects wish to do, their software-defined data plane designs can be realized in mid-range Kintex FPGAs, high-end Virtex FPGAs, Zynq SoC FPGAs, or a mixture thereof.
The SDNet environment allows architects to provision exact services from core to edge.
The end result is for the high-level specifications captured by the system architects to be optimized and compiled into data plane processing hardware in the form of Xilinx FPGAs and SoCs, all without the architects having to know anything about FPGA architectures or design techniques. This open-ended framework also facilitates the inclusion of unique and differentiated customer IP. Most importantly, the high-level SDNet specification is portable and scalable across line rates from core to edge applications.
I remember capturing ASIC designs by hand as gate-level schematics in the 1980s. The move to capturing the design at a higher level of abstraction in a hardware description language (HDL) and then using logic synthesis to convert this specification into the final gate-level implementation was revolutionary. It allows us to create larger designs than would be possible by hand, and to explore different implementation scenarios so as to decide on the optimal solution.
Similarly, by raising the level of abstraction, the SDNet environment makes it possible to experiment with different design scenarios and to create larger, more complex designs that would simply not be possible (or, at least, commercially feasible) if we were coding things by hand.
Now I'm wondering what else might be coming our way. Can you think of any other application area that could benefit from this sort of approach -- e.g., a higher-level specification capture-and-compile environment sitting on top of the Vivado Design Suite?
— Max Maxfield, Editor of All Things Fun & Interesting