MOUNTAIN VIEW, Calif. — Semiconductors have a bright future even though they are becoming increasingly costly and complex to make for a consolidating set of players, according to a panel of experts at the GSA Silicon Summit here.
However, panelists took a narrow view of the future for fully depleted silicon-on-insulator (FD SOI) technology as an alternative to FinFETs, and they were mixed at best in their opinions on a shift to 450mm wafers.
The panel comes at a time when some industry watchers are calling for a shift to FD SOI, predicting a rise in cost per transistor. Others argue 28nm was the last turn of the crank for Moore's Law.
Next to Moore's Law the industry has had a second constant, said Joseph Sawicki, general manager of the design-to-silicon division at Mentor Graphics. Whatever technology is two nodes away will be "impossible," he said.
He noted past concerns about the submicron barrier and getting 90nm chips at desired yields. "We are at another one of those stages today, but that's cold comfort [given] real challenges ahead," he said noting high-k metal gate transistors lasted for just two nodes and today's FinFETs likely will be short lived, too.
Although panelists expressed optimism, "you have to have a lot of caution, too, because now we have five or six reasons why the node that's two nodes from now won't work -- we used to have just one reason," said Robert Aitken, a fellow in R&D at ARM.
The good news is lab work suggested FinFETs can be built at 7nm and work on "gate all around" structures look promising for a 5nm node, said Adam Brand, managing director of transistor technology at Applied Materials. "We really haven't approached the atomic level – there's a plausible pathway to keep making things a lot smaller," he said.
Among the challenges Brand noted, "a lot of new materials will come in at 10 and 7nm to allow different structures to keep functioning."
Defect rates for new nodes are actually declining faster than ever, said Peter Huang, a vice president of advanced technology support and marketing for TSMC. "We have a steeper D0 reduction [at 20 and 16nm] than on 28nm -- the learning cycle can be accelerated," Huang said.
Yields at 28nm were better than expected with "gate oxides scaling for the first time in two or three generations," said John Kibarian, chief executive of PDF Solutions. "Due to inventiveness in the industry, yield on a per-die and per-layer basis has gotten better," he said.
The improvements have come, in part, from more sweat and money as companies are "investing in nodes early for longer than before," Kilbarian said. "We see the amount of time spent on a node versus the time the product sits in the node is at a 3-to-1 ratio at this point," he added.
Next page: Economics, FD SOI and 450mm wafers