PORTLAND, Ore. — Cadence Design Systems Inc., based in San Jose, Calif., intends to acquire Jasper Design Automation Inc. of Mountain View. for $170 million in cash, thus adding Jasper's highly regarded formal analysis toolkit -- verification apps built on the JasperGold platform -- to Cadence's already comprehensive System Development Suite.
Cadence's System Development Suite already includes debug analysis, simulation, acceleration, emulation, and prototyping as well as Cadence's own versions of formal and semi-formal solutions. Cadence claims the complementary tools from Jasper, combining dynamic and formal techniques, will greatly enhance embedded processor verification for systems-on-chip (SoC).
"Jasper's technology in formal analysis, which targets very complex verification challenges that are hard to address with our dynamic tools, will complement Cadence's System Development Suite -- our verification platform -- to create what we believe is the most comprehensive platform available today for verification and design," said Craig Cochran, vice president of corporate marketing at Cadence, in an interview with EE Times.
Cadence and Jasper already share many top-tier systems, semiconductor, and intellectual property (IP) companies, making it only natural for Cadence to integrate its simulation-based verification tools with Jasper's formal analysis verification tools.
"And as the leader in that space this acquisition will bring additional opportunity to Cadence," says Cochran. "This is not just a strategic move by Cadence, because we have key top-tier customers that we share with Jasper that have asked us to add Jasper to our portfolios, so this will benefit those customers as well."
Formal analysis is the fastest growing market segment within verification, says Cochran:
The biggest challenge to developing a system-on-chip today is verification, which comprises about 70 percent of the effort. What we are seeing now is increasing IP design complexity and the complexity of integrating IP into systems-on-chip is driving that verification problem to even higher complexity. Our customers are dealing with that by turning to multiple complementary verification approaches.
Cadence already has rudimentary formal analysis tools, as well as semi-formal tools that combine simulation with formal analysis, but Jasper's deeper dive into the formal analysis space should add dimension to Cadence's verification apps.
"Jasper's tools are complementary to ours," says Michał Siwinski, vice president of product marketing. "Jasper has done a fantastic job targeting the more expert use model, making sure the formal is helping define the very complex problems and adding specific apps for specific problems like connectivity."
Cadence also claims the two companies have complementary offerings to customers using ARM cores in their designs.
"One of the things we have been getting a lot of traction on lately at Cadence is building a verification environment around ARM solutions," Siwinski told us, "and that is something that Jasper has also been working toward by not only having ARM as a customer, but also enabling ARM-based SoCs, particularly for mobile and consumer, but also for memory and storage."
Cadence will use available cash, along with its revolving credit lines, to raise the $170 million to close the deal, if all goes well, in the second quarter of fiscal 2014. As of December 31, 2013, Jasper had approximately $24 million in cash, cash equivalents, and short-term investments.
— R. Colin Johnson, Advanced Technology Editor, EE Times