Updated on May 7, 2014 to remove a technical error.
TORONTO — A technology in development for more than two decades may have the answer for extending the end of Moore’s law, according to a company coming out of stealth mode.
POET Technologies derives its name from “Planar Opto-Electronic Technology,” which is its gallium arsenide (GaAs) process used to build electrical, optical, and electro-optical integrated circuits. It is the result of research spearheaded by Geoffrey Taylor, the company’s chief scientist, who has been directing its development and is concurrently a professor of electrical engineering and photonics at the University of Connecticut, where the company houses its research and development facilities.
Geoffrey Taylor, POET Technologies' chief scientist
Taylor’s three decades of experience in design and development in electronic and optical device physics, circuit design, and opto-electronic technology, materials, and applications has been critical to the development of the POET platform. As part of a presentation to EE Times, the company outlined the heart of POET Platform -- a patented materials system that supports monolithic fabrication of integrated circuits containing active and passive optical performance analog and digital elements.
The full POET process also includes a “Planar Electronic Technology” electrical subset that can support CMOS, Bi-CMOS, and bipolar device fabrication, and offers cheaper, simpler process and fabrication options for applications that don’t require optical.
Semiconductor performance has historically improved at a logarithmic rate because transistors have shrunk in size, allowing more transistors to be packed into a semiconductor chip, notes Taylor. Moore’s Law established the idea that the number of transistors in a chip doubles every 1.5 to 2 years, thus increasing capabilities of electronic equipment, but the challenge is that as transistors become smaller, the cost of reducing size while increasing speed becomes more expensive, and eventually uneconomical.
There’s been much discussion about the demise of Moore’s Law. Last year, one expert suggested it would be dead as soon as 2020 at the 7 nm node, while MonolithIC 3D’s Zvi Or-Bach recently wrote that 28 nm is actually the last node of Moore’s Law because, even though it’s possible to make smaller transistors and more of them can be packed into the same-size die, costs can’t continue to be reduced. Last year, Broadcom’s CTO predicted that standard CMOS silicon transistors will stop scaling around 5 nm, and everything will plateau.
POET’s view is that recently developed 3D silicon semiconductors stacking multiple chips and other silicon high-performance compound devices are very expensive to make and only offer moderate improvements over incumbent chips. One of the advantages POET presented about its process is that it can leverage existing CMOS chipmaking equipment, and it is fully compatible with existing semiconductor design and manufacturing flows. Taylor says POET’s benefits are analogous to the benefits of the first silicon integrated circuits, in that it eliminates connectors, solder joints, assembly, and multiple packaging steps while decreasing size, cost, complexity, and power.
POET expects commercial applications for the process to include CPUs, memory, and processor-to-processor optical interconnect. A POET memory cell can concurrently support SRAM, DRAM, and NVRAM devices, and offers lower bit error rates than silicon-based memories, according to the company.
To validate the POET process, the company has partnered with a third-party international defense services company, which has researchers working on its continued development. The partnership has successfully reproduced the POET technology through production and testing of the critical elements of the POET platform sub-process steps for transistors.