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Novel, Inexpensive 3D Chips Funded by SRC

5/7/2014 09:40 AM EDT
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R_Colin_Johnson
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Re: That would be ideal for power gating switches...
R_Colin_Johnson   5/7/2014 11:34:42 AM
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Of course, stacking memory is the most obvious application, but I'm sure that when designers put on their thinking cap they'll find many more useful applications of having active devices within the metalization layers--just like you did.

vlsi_guy
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That would be ideal for power gating switches...
vlsi_guy   5/7/2014 11:21:52 AM
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Assuming idrive is good, leakage is comparable or better, and low source/drain resistance we could have these power gating (e.g., header switches) up near the top of the BEOL. Rather then now, where we have to go all the way down to FEOL then post switch route back up to upper layers just to distribute current back down to functional devices.

Sign me up :-)

 

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