TORONTO -- The growth of mobile devices that require smaller components is making manufacturing more complex as geometries shrink. A number of vendors are addressing process technologies through different techniques as the industry gears up for a transition to 3D NAND and looks to meet market demand for more efficient, lower-power components.
Ziptronix and EV Group recently announced that they have achieved submicron post-bond alignment accuracy on DRAM customer-provided 300 mm wafers. The process combines Ziptronix's Direct Bond Interconnect Hybrid Bonding technology with an EVG facility-based SmartViewNT Automated Bond Alignment System for universal alignment.
Paul Enquist, CTO and vice president of engineering at Ziptronix, told us that its DBI Hybrid Bonding is a conductor/dielectric bonding technology that includes a variety of metal/oxide and/or nitride combinations. The technology does not use adhesives, and it allows for room temperature dielectric bonding, which he said lowers the total cost of ownership. Unlike in copper wafer bonding, one of the common technologies used by the semiconductor industry for 3D integration, the bond occurs between both the dielectric and the conductive surfaces. Enquist said this bonds the entire substrate interface area.
The approach can be used to manufacture large-volume fine-pitch 3D integrated circuits for a number of applications, including stacked memory, advanced image sensors, and stacked systems-on-chip, Enquist said. His company's DBI technology requires the right alignment and placement tool with the ability to scale. Alignment has been a key focus, and that's where EVG's SmartViewNT bond aligner comes into play.
Dr. Thomas Uhrmann, deputy head of business development at EVG, told us SmartViewNT is a proprietary method of face-to-face wafer-level alignment, which is key to achieving the necessary accuracy in multiple wafer stacking. Improving alignment to reach sub-micron accuracies is the most important factor, he said, but EVG's fully automated wafer bonders support all processing steps for hybrid bonding, such as cleaning, plasma activation, alignment, and wafer bonding.
Enquist said scaling is important, but so is having a very fine pitch connection, whether it's for image sensors or memory. In image sensors, for example, some architectures require one connection for every pixel, and pixel pitches are already scaling to less than one micron. "It's important to be able to have a technology that can scale to sub-micron pitch, which is what the DBI Hybrid Bonding is able to do."
Stacking technology is just one many components required for the transition to 3D, he said. Another factor in making the transition economically viable is being able to use current tools. Ziptronix's collaboration with EVG has allowed it demonstrate that its bonding process doesn't require completely new equipment. "Ziptronix has a bond technology that has many applications, whereas EVG has the business to build tools that can align place makers that have high accuracy." Customers like to see results, especially with their wafers, on production tools, he said.
Though customers do not have to use EVG tools, Uhrmann said fully integrated bonding tools allow them to control the entire process and value chain for the hybrid bonding.
The Ziptronix process, combined with EVG's technology, is one of many new techniques designed to address the transition to 3D and meet market demands for smaller, lower-power components with improved performance. Both SanDisk and Toshiba recently announced new process technologies, and POET Technologies recently went public with a gallium arsenide process.