Breaking News
News & Analysis

DCD's D16950 UART Soft IP Core for FPGAs & ASICs

6/11/2014 04:26 PM EDT
8 comments
NO RATINGS
More Related Links
View Comments: Threaded | Newest First | Oldest First
DrFPGA
User Rank
Blogger
Efficiency
DrFPGA   6/12/2014 4:38:08 PM
NO RATINGS
The 128byte FIFO and the hardware support for CTS/RTS (that keeps the CPU from neededing to take action) are excellent efficiency enhancers. I just want the data to flow with as little CPU intervention as possible. Just set-up the buffer and go do something else. Cool.

Max The Magnificent
User Rank
Blogger
Re: Efficiency
Max The Magnificent   6/23/2014 9:42:14 AM
NO RATINGS
@DrFPGA: The 128byte FIFO and the hardware support for CTS/RTS...

It's funny -- we're so used to thinking in terms of megabytes and gigabytes (re a computer's main memory) that we forget how much difference a few bytes can make in something like a judiciously-placed FIFO

Sanjib.A
User Rank
CEO
Helping in tackling obsolescence
Sanjib.A   6/22/2014 2:18:45 AM
NO RATINGS
I guess another advantage of such IPs getting available for FPGA/SoC platforms would be to make life easier for tackling obsolescence of the original ICs. By making the clone of such popular but matured ICs based on programmable platforms, it helps in reducing the re-design efforts for extending the life of the product for much longer period and makes the development cycle shorter.

Max The Magnificent
User Rank
Blogger
Re: Helping in tackling obsolescence
Max The Magnificent   6/23/2014 9:40:16 AM
NO RATINGS
@Sanjib: I guess another advantage of such IPs getting available for FPGA/SoC platforms...

It also makes it easier to prototype in an FPGA before committing to an SoC

DrFPGA
User Rank
Blogger
Re: Helping in tackling obsolescence
DrFPGA   6/23/2014 11:49:03 AM
NO RATINGS
SoC, SoC FPGA, ASIC, ASSP- how my head hurts. I think you may need to do another blog on the alphabet soup we have created around our various Programmable Logic Devices...

Do you have a taxonomy you feel strongly enough to blog about? Maybe we need to put naming things back in the hands of engineers and take this mighty power away from the marketing types...

Max The Magnificent
User Rank
Blogger
Re: Helping in tackling obsolescence
Max The Magnificent   6/23/2014 12:39:17 PM
NO RATINGS
@DrFPGA: SoC, SoC FPGA, ASIC, ASSP- how my hear hurts. I think you may need to do another blog on the alphabet soup we have created around our various Programmable Logic Devices...

Actually, that would be a good one -- leave it with me :-)

DrFPGA
User Rank
Blogger
Re: Helping in tackling obsolescence
DrFPGA   6/23/2014 1:07:48 PM
NO RATINGS
The future is in your hands...

Max The Magnificent
User Rank
Blogger
Re: Helping in tackling obsolescence
Max The Magnificent   6/23/2014 1:22:15 PM
NO RATINGS
@DrFPGA: The future is in your hands...

I just have to remember to make sure I use my power only for the good :-)

August Cartoon Caption Winner!
August Cartoon Caption Winner!
"All the King's horses and all the KIng's men gave up on Humpty, so they handed the problem off to Engineering."
5 comments
Top Comments of the Week
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Times on Twitter
EE Times Twitter Feed
Flash Poll
Radio
LATEST ARCHIVED BROADCAST
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.