PORTLAND, Ore. — Intel unveiled its many-integrated core (MIC) roadmap to expand the high-performance computer market at the International Supercomputer Conference (ISC-14) in Leipzig, Germany, June 22-26. The multi-faceted unveiling revealed the details of a new version of its massively parallel processor -- the Xeon Phi -- as well as a new interconnection fabric based on Intel's silicon photonics advances, and an educational program designed to give every new programmer on the planet the opportunity to learn how to code for parallel processors.
"In just 16 years, we've seen the fastest supercomputer in the world at 3 teraflops migrate down to a single socket," Charles Wuischpard, vice president and general manager of Intel Workstations and High Performance Computing Data Center Group told EE Times in a conference call.
Intel has been talking about a new version of its massively parallel Xeon Phi processor -- currently with 60 cores per chip -- but at ISC-14 unveiled many more, but not all, of the details about the new chips, which will be available in the second half of 2015. Its current-generation Xeon Phi is a 1-teraflop chip cast in 22 nanometer CMOS and sold on a PCIe board in several versions. The Green500 list pronounced it the most power efficient parallel processor in the world. The Top500 supercomputer list just announced the Xeon Phi powered Tianhe-2 (Milky Way 2) supercomputer at the National Supercomputing Center in Guangzhou, China as the fastest in the world for the third time running.
"We have a new Xeon Phi processor coming in the future called Knights Landing," said Wuischpard. "The first thing to note is that it will be 3 teraflops in a single package, which will be available in the second half of 2015, with at least as many processors, but based on the Silvermount architecture and connected by a low-latency mesh."
Intel predicts that high-performance computers will grow at a rate of 20% per year as prices drop, inducing more segments to purchase them.
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The previous MIC processor -- called Knights Corner -- was based on a special microarchitecture created just for it, but the new-generation Knights Landing Xeon Phi will be based on Silvermont modified for Intel's 14 nanometer process. The Silvermont architecture has also been heavily modified to add key features, such as a AVX512 vector processor and four threads per core, versus the current Silvermont, which has no AVX512 support and just one thread per core.
"The next generation of Xeon Phi processors will get more than just a processor speed-up. It will feature more than just a faster processor, but more integration of memory and greater processor power efficiency," says Wuischpard.
Other details provided by Wuischpard claimed three times the single-thread performance of the existing Xeon Phi -- 16 Gbytes of on-package memory connected by DDR4 to a special Micron Hyper Memory Cube designed in collaboration with Intel. Wuischpard also claims the Silvermont Xeon Phi will take up one-third of the space, be five times more power efficient, and yet binary compatible with the existing Xeon Phi.
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