SAN JOSE, Calif. — The semiconductor road map is becoming as narrow and twisting as a mountain road, according to executives at two capital equipment companies. Chip vendors face higher costs and complexities due to tighter margins, new processes, and materials at 20 nm and beyond, they say.
In logic, foundries and their fabless customers have yet to settle on a new set of design rules. In memory, NAND flash has started a shift to 3D design other chips are likely to follow in some form, and DRAM faces a major materials shift, probably in 2015.
At 20 nanometers, the overlay budget of about 6 nm will shrink to about 4.5 nm while specifications for critical dimensions will narrow from 3 nm to 2 nm, says Brian Trafas, chief marketing officer at KLA-Tencor. He also predicts a 30% increase in process control spending between the 28 nm and 20 nm nodes to handle the requirements for multiple lithographic patterns needed to define some mask layers.
Chipmakers are using multi-patterning in four to ten mask layers starting at 20 nm and the follow-on node. In addition, these nodes are adding on a number of new deposition and etch steps, Trafas tells us.
Additional mask costs alone could be as much as $3 million for each chip design based on merchant costs of about $150,000 per mask, says Chris Bencher, a distinguished member of technical staff in the office of the CTO at Applied Materials. "Between the 45 nm and 16 nm nodes, chipmakers are going from 50 to 70 masks per device."
Flash chip designers pioneered ways to use multi-patterning while not raising costs to make small, but regularly shaped, features for generally small chip dies. However, logic designs use larger dies and want irregular patterns that help boost performance and lower power, says Bencher.
As a result, "in logic, there's a battle between the designer and lithographer to find compromises that don't add too many masks and delay the need for double or triple patterning," says Bencher, who is considered Applied's lithography guru. In short, logic chip designers "are in a world of hurt."
"Intel is uniquely positioned because they have the designers and lithographers both in-house and can drive compromises internally. Foundries are more challenged: How do they tell customers they don't want them to put a jog in metal-layer 1?"
Flash designers showed ways to use two masks per active layer, but the techniques require maintaining a common set of critical dimensions across a chip. Logic designers want to vary these dimensions to raise performance and lower power, forcing a need for three masks per critical layer, he says.
Next page: Leapfrogging to 16/14 nm