PORTLAND, Ore. -- For over two decades IBM has tried nearly every possible way to a make a tiny 1.4-nanometer carbon nanotube the successor to the silicon transistor channel. Today the smallest silicon transistors are already achieving atomic limits -- a 4-nanometer silicon transistor channel, for instance, would consist of about 20 atoms. To go to the next silicon generation, all sorts of imperfections and uneven doping problems are facing the further downsized silicon transistors. If IBM, or others -- in fact China is now leading in nanotube research -- can perfect the 1.4-nanometer transistor channel, then Moore's law can keeping marching forward a little while longer. If not, a whole new paradigm may have to be invented.
Relatively recently, the nanotube transistor guru, IBM Fellow Phaedon Avouris, found greener pastures to explore in plasmonics and photonics. The nanotube team is now led by Wilfried Haensch at the T.J. Watson research lab of Yorktown Heights, N.Y. Haensch is facing the same problem that Avouris has been facing, that of how to position such impossibly small components into nice neat straight lines for transistor canals. He has a few new tricks up his sleeve, some put there by James Hannon, head of IBM's molecular assemblies and devices group.
The source and drain electrodes cover the carbon nanotubes channel, all controlled by the same local back gate.
One new idea is not to depend on just a single nanotube, but to use multiple nanotubes for a transistor channel, hoping that at least a few work. In simulations, they have lined up six relatively parallel 1.4-nanometer-wide and 30-nanometer-long nanotubes with a generous spacing of 8-nanometers between them. The ends are embedded in the source and drain of the nanotube, leaving 10-nanometer channels suspended over the gate electrode at the bottom of the stack. Their next simulation will be to label the substrate and nanotubes chemically for correct alignment, then strip away the chemicals for a real finished chip -- an IBM Power7.
Haensch tells EE Times:
The six-tube device structure came out of complex optimization process that models the performance of an entire microprocessor, in this case an IBM Power7 chip. The optimizer varies the layout of the device, including the wiring, and predicts the system performance.
The International Technology Roadmap for Semiconductors (ITRS) calls for the 5-nanometer node to be reached by 2019, so IBM has set is goal for nanotube transistors by 2020.
IBM has recently fabricated circuits with as many as 10,000 carbon nanotube transistors (CNTs). Simulations of that design predict performance five times as fast as silicon. He tells EE Times:
The device will incorporate 5 to 6 CNTs [per channel]. The CNTs will have a diameter around 1.4 nanometers. The diameter is chosen to give the desired band gap. In order to achieve a performance advantage over silicon, the device must be small. The model suggests that we need a nanotube pitch (CNT-CNT distance) of about 8 nanometers. The channel (or gate) length (Lg) will be about 10 nanometers, with source (S) and drain (D) contacts also about 10 nanometers long. LBG is the local bottom gate. That is the electrode that controls the channel conduction. We have already built devices with less than 10-nanometer channel lengths. The 10 nanometer CNT pitch is difficult to achieve due to the limitations of patterning methods, but we have published results with 200-nanometer CNT pitch. We have also built multi-CNT devices (with 2, 3, 4, and 6 CNTs). As expected, the current is larger, but the variability of the devices is reduced due to the averaging effect of having multiple CNTs in the channel.
According to Haensch, there are several hurdles at need to be surmounted to meet the 2020 dead line, not least of which is separating the semiconducting from metallic nanotubes, which has been an enduring problem from the beginning over two decades ago. He tells EE Times:
The major hurdles for a successful CNT VLSI technology [are] placement control and degree of purity of the carbon nanotubes. To meet both challenges, different approaches are pursued. IBM favors [depositing] a highly purified population of CNTs on a wafer at predetermined locations defined by chemical markers. This way, randomness due to elimination of metallic CNTs is significantly minimized, and the distribution of the CNTs across the wafer can be very well controlled.
IBM is committed to try to meet the 2020 deadline, but admits that all major hurdles much be surmounted to keep the project alive after 2020. Otherwise other techniques such as spintronics, which is less mature today, will likely overtake nanotube research then.
— R. Colin Johnson, Advanced Technology Editor, EE Times