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13 Things I Heard at Semicon West

7/11/2014 09:00 AM EDT
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rick merritt
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What did you hear?
rick merritt   7/11/2014 10:29:27 AM
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There was a ton of activity at the event and many talks I could not get to, so what did I miss?

alex_m1
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Re: What did you hear?
alex_m1   7/16/2014 6:09:27 PM
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Rick, a guy from zvi orbach's company talked about 3d chips as a strong way to fight defects. Self assembly and  Molecular Imprints suffer strong defect rate, but at least they have the resolution. I wonder how well a combination will to solve the defect issue will work cost wise ?

resistion
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Re: What did you hear?
resistion   7/16/2014 6:48:47 PM
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How would 3d help defects? If redundancy, still need a defect-free die or part.

alex_m1
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Re: What did you hear?
alex_m1   7/17/2014 2:43:53 AM
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Resistion: the way i understood it , you build 2 equivalent layers on top of one another, And for gate(or cell) you choose which layer 2 use after manufacturing - using boundary scan for detection and e-beam for the repair. more details in [1].


Assuming defects are uncorrelated between layers(big assumption), this greatly decreases you defect probability.

 

[1]http://www.monolithic3d.com/ultra-large-integration---redundancy-and-repair.html

resistion
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Re: What did you hear?
resistion   7/17/2014 5:51:49 AM
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Thanks, alex_m1. The concept of this repair layer sounds interesting, but of course, it's still cheaper to have all the layers within defect tolerances to begin with (so then you could go on to heterogeneous integration).

alex_m1
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Re: What did you hear?
alex_m1   7/17/2014 12:54:33 PM
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@resistion:i think the case of 3-4 real logic layers + 1 repair layer might be interesting economically and might offer enough defence against defects to make those methods(self assmbly,imprints) useful.

 

resistion
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Re: What did you hear?
resistion   7/18/2014 2:18:04 AM
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Ok, but if there is an overlay error issue, especially from the new patterning technologies, then there's nothing that can be done.

alex_m1
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Re: What did you hear?
alex_m1   7/18/2014 4:28:53 AM
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What's an overlay error?

rick merritt
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Re: What did you hear?
rick merritt   7/18/2014 8:52:26 PM
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@Alex: I am no expert, but I assume it is when you are doing a second litho pattern for a critical dimension and it does not line up within given tolerances with the previous pattern.

Someone correct me if I am wrong.

resistion
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Re: What did you hear?
resistion   7/19/2014 6:33:31 AM
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It's the right idea, it looks like you are referring to the example of double patterning using two exposures, for a single layer. More generally, overlay is referring to the interaction between successive layers, so that they link up properly. Multiple exposures does have higher risk than single exposure. But these recent new single-exposure technologies have their own sources contributing overlay error. Meanwhile multi-patterning is heading toward self-aligned approaches.

resistion
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Re: What did you hear?
resistion   7/19/2014 6:25:50 AM
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When patterning a first layer, the features deviate from their positions within a tolerance. Then when the next layer is patterned over the first layer, those features also deviate from their positions within a tolerance. If the tolerances are followed, there should be no risk of broken connections, line shorts, etc.

resistion
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Thanks for the summary
resistion   7/11/2014 11:25:10 PM
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Nice crisp summary, for those of us who can't go, perennially.

resistion
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Key takeaway
resistion   7/11/2014 11:42:13 PM
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"No matter what Intel says, Moore's Law is slowing down," said Bob Johnson, a semiconductor analyst for Gartner. "Only a few high-volume, high-performance apps can justify 20 nm and beyond." He sees problems ahead for logic chips in general. The smartphone market is nearing saturation, ultramobiles are canabalizing PCs, and "logic is running out of gas."

If logic is getting affected, that's a really big problem.

chipmonk0
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Re. Item 5 : Heard the one about Snapdragon ?
chipmonk0   7/15/2014 8:26:20 PM
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Is that such a big deal ?

a 2 x 64 bit bus carrying 25 GByte/s for LP DDR ( Dual Data Rate ) means a Clock Rate of 800 MHz, not at all unusual for LP DDR 3, it works even with conventional lossy Packages.

Apple has been using them for the 5s since last Fall, had to shrink Package interconnect pitch to accomodate wider channels, but that's still a conventional PoP package. SK Hynix claims their LP DDR 3 can run at Clock Rates double that but have n't seen a SoC - DRAM module packaged in conventional PoP working at 1.6 GHz yet.

We do special loss - less Packages that clean up the Eye Diagram even at much higher Clock Rates for very high Bandwidth and low Power loss w/o having to drill any TSVs into live chips.

rick merritt
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EUV update
rick merritt   7/16/2014 10:09:19 PM
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ASML announced in its quarterly earnings call yesterday that EUV throughput with at least one customer is now up to 200 wafers/day.

Of course its wafers/HOUR which is really key. Waiting to hear back if they have any news on that.

The Q1 report was ~37 w/h and the target for commervcial use is more like 100+

resistion
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Re: EUV update
resistion   7/16/2014 11:16:19 PM
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The units for EUV throughput are really wafers per day, and 200 is the current capabilty: http://seekingalpha.com/article/2318615-asml-holdings-asml-ceo-peter-wennink-on-q2-2014-results-earnings-call-transcript?part=single

They would like to go to 500 this year and eventually 1500 wafers/day. Their immersion meanwhile already does >5000 wafers/day.

resistion
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Re: EUV update
resistion   7/26/2014 10:52:00 PM
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The reason they changed to wafers per day, is not only that they cannot get enough wafers per hour, but also the EUV machine is not (or cannot be) up 100% of the day. So even if the WPH is quite reasonable, with the extended downtime, it still reduces the throughput, that is measured in wafers per day.

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