Designing system-on-chip (SoC) devices becomes increasingly complex with every new process node. Tasks that were barely manageable at the 40nm node require the ability to handle huge capacity and complexity at the more advanced nodes.
Parasitic extraction hasn't been simple for a long time, but technologies like double and triple patterning are raising things to a new level of complexity. On top of all this, we now have to account for extremely complex 3D structures, including FinFET transistors and full-up 3D ICs featuring through-silicon vias.
To address these issues, Cadence has announced its Quantus QRC Extraction Solution. Based on a massively parallel architecture that is scalable to hundreds of processors, Quantus QRC delivers exceptionally fast runtimes coupled with consistent accuracy between single- and multi-corner extractions, thereby helping to accelerate design signoff and reduce both time to silicon and time to market.
Of course, speed and performance are meaningless without accuracy. Quantus QRC has been fully certified by TSMC to its Golden data for 16nm FinFET designs.