There are various tools and techniques available to ASIC/SoC development teams to verify their designs. At one end of the spectrum is software simulation, which is relatively inexpensive and which offers tremendous visibility into the design, but which is capacity-limited and performance-limited, and is really suitable only for block-level verification.
At the other end of the spectrum is hardware acceleration and emulation, which provides hardware/software co-verification and system-level verification prior to post-silicon bring-up. Hardware acceleration/emulation offers tremendous capacity and advanced debug capabilities, but it can be tremendously expensive. Also, even though a hardware accelerator/emulator can offer orders of magnitude speed increase over software simulation, it is still performance-limited. In the case of Cadence's Palladium series of high-performance, single-system, multi-user accelerators/emulators, users typically achieve performance in the 1.0 MHz to 1.5 MHz range.
Yet another solution is that of FPGA-based rapid prototyping. This is significantly cheaper than emulation and offers much higher performance, but debug capabilities are usually more limited. Also, there can be a lot of work involved "massaging" the ASIC/SoC RTL into a form suitable for use in the FPGA-based rapid prototyping platform. This includes handling memories, inserting debug facilities (in the form of virtual logic analyzers), partitioning the design across multiple FPGAs, and so forth.
All of which leads us to the fact that Cadence now offers a "continuum of verification engines." In addition to its Palladium series of accelerators/emulators, Cadence has just announced its Protium FPGA-based next-generation rapid prototyping platform, which supports a combination of transaction-level and RTL verification.
For those users who already own a Palladium, the Protium -- which is based on Xilinx Virtex-7 2000T 3D FPGAs and which supports up to around 100M gates -- can be used in an adjacent flow to the Palladium. In fact, the Protium can reuse around 80% of an existing Palladium environment.
Of particular interest is the fact that the Protium offers adjustable levels of performance depending on how much effort the users wish to employ. In the case of a fully automatic usage model, the Protium environment will automatically perform clock-tree transformations, ASIC/SoC memory mapping, design partitioning, and FPGA place-and-route. In this case, users can expect performance in the 3 MHz to 10 MHz range.
If the users provide some amount of guidance with regard to partitioning, logic replication, clock tree simplification, directly connecting bulk memories, and FPGA place-and-route options and constraints, then they can expect performance in the 10 MHz to 30 MHz range. If the users wish to go further and employ black-boxing techniques, including things like FPGA-specific optimizations, then they may be able to exceed 100 MHz.
Not surprisingly, as illustrated in the above graphic, all sorts of numbers are flying around with regards to capacity and performance and compile times and bring-up times. To really get to grips with these values, click here to visit the Cadence website.
— Max Maxfield, Editor of All Things Fun & Interesting