PORTLAND, Ore. — Movidius Ltd. invented a system on chip (SoC) it calls a vision processing unit that defines a new product category, due to its emulation of human vision functions. Its VPUs provide visual awareness and perform computational photography. They are designed to go between a mobile device's image sensor (camera) and its application processor.
The first-generation chip, the Myriad 1, was used in Google's Tango, but now Movidius has announced its second-generation device, Myriad 2. It says the new device is 20 times faster than the one used in Google's Tango, providing two teraflops of 16-bit operations from a chip measuring just 6.5 mm square.
"Myriad 2 is completely dedicated to this new era of computational cameras," Movidius CEO Remi El-Ouazzane told EE Times. "With it, we've achieved 20 times the power efficiency over Myriad 1, meaning we have 20 times the performance [two teraflops] for the same amount of power consumed, or the same performance for 1/20th the power consumed."
The new Myriad 2 vision processing unit (VPU) measures just 6.5 mm on each edge and is packaged in a 0.4 millimeter pitch 225 ball grid array (BGA) package with 1 Gbit of low-power double data rate (LPDDR II)
synchronous random access memory.
The Myriad 1 was originally designed as a co-processor for smartphones and other mobile devices that already have an application processor, but the Myriad 2 can also replace the application processor for simple wearable applications, due to the presence of two on-chip high-level reduced instruction set computers (RISCs).
One RISC core runs the real-time operating system and one can run real-time application code. In addition, the Myriad 2 has 12 Streaming Hybrid Architecture Vector Engines (SHAVEs), or four more than its predecessor. SHAVEs combine the best features of RISCs, digital signal processors, graphics processor units, and very long instruction world architectures and can handle both fixed and floating-point data formats. The SHAVEs surround a low-latency memory fabric that accounts for the chip's low power consumption (500 milliwatts) by virtually eliminating the usual time- and power-consuming tasks of buffering data streams.
Movidius Myriad-2 from Gary Brown on Vimeo.
Also, Movidius has added 20 hardware accelerators -- called atomic-imaging vision engines -- for frequently used vision-processing tasks. Also on the chip are 12 mobile industry processor interface (MIPI) channels and the assorted peripheral interfaces -- including Ethernet, USB, SPI, I2S, LCD, and UART. The Myriad 2 measures just 6.5 mm square and is packaged in a 0.4 mm pitch 225 ball grid array package with 1 Gbit of low-power double data rate (LPDDR II) synchronous random access memory.
The new category of VPU connects directly to the imager,
not the application processor.
"The Myriad 2 is 20 times faster than the Myriad 1 because of three things," El-Ouazzane said. "The first is that Myriad 2 has 50% more programmable cores than Myriad 1 -- 12 instead of 8. Secondly, instead of running at 180 MHz in the 65 nanometer process technology used for Myriad 1, the Myriad 2 is now running at 600 MHz in 28 nanometer process technology. And the third reason -- which gives the biggest bang for the buck -- is that Myriad 1 used only programmable cores, but by slightly changing the architecture, we have added more than 20 very high performance hardwired configurable accelerators for imaging and vision tasks, allowing us to deliver more than two teraflops of 16-bit performance."