SANTA CLARA, Calif. — Samsung announced a three-bit per cell version of its 128 Gbit vertical NAND flash is weeks away from shipping. It also launched an industry effort to tap into flash controllers for a variety of storage and compute tasks.
Within a month, Samsung could start shipping solid-state drives using new 128 Gbit V-NAND chips with 32 layers and three bits per cell. It promises to deliver twice the capacity at 40% less power than SSDs with planar NAND, said Bob Brennan, head of the company's memory lab in San Jose, speaking in a keynote at the Flash Memory Summit here.
Brennan was not able to give performance, power consumption, or endurance details for the new flash design. Samsung announced its first V-NAND products at the event last year, a 24-layer design using two bits per cell. It announced an upgrade to a 32-layer design last month.
Chipworks posted this week a detailed analysis of Samsung's V-NAND.
Maintaining the same cell-to-cell interference was a top challenge of the latest design, Brennan said. He predicted 256 Gbit chips will arrive in 2015 and said the company will eventually get to 100-layer Tbit chips.
"Vertical NAND has now crossed the threshold of cost, and we will continue to scale dollars per Gbyte for years to come," Brennan said.
Separately, Brennan showed preliminary results of how flash controllers could be used to lower latency and improve performance on SSDs. The lab results encouraged the Korean giant to launch an industry initiative to leverage unused capabilities of flash controllers to handle a variety of storage and compute tasks.
A new working group in the Storage Networking Interface Alliance will work on an API for the so-called intelligent storage initiative. The NVMe group that developed a new interface for SSDs riding the PCI Express bus will also start a working group in the area, Brennan said in a brief interview with EE Times after his keynote. The T10 and T13 storage standards groups may also work on the initiative.
"We decided over the last couple months to open this up to the industry," Brennan told EE Times "We took a risk putting this out before we have all the questions answered, but we don’t think it's right to invite collaboration when you have a fully baked solution," he said.
Making data about the performance of flash chips available to storage applications is a first step. The initiative ultimately aims to open up flash controllers as a distributed resource for any tasks in a datacenter, he said.
"There will be hundreds if not thousands of SSDs in the datacenter over time with their processors only busy at peak times," he told attendees here.
The initial work took place in Samsung labs in Korea and San Jose using an SSD with a serial ATA interface. Samsung has not decided yet whether it will turn its lab work into a product, Brennan told EE Times.
The news came just minutes after a datacenter manager from China's Alibaba called for closer data links between flash memory chips and applications using them. "This is the sort of applications-centric approach we have been seeking," Wu Peng, the Alibaba keynoter, told EE Times after the Samsung talk.
Samsung got more consistent I/O operations/second linking flash and apps data via its controller on a SATA SSD (above) and got low latency with fewer IOPS when intelligently checking with apps about when to do garbage collection (below).
— Rick Merritt, Silicon Valley Bureau Chief, EE Times