A very significant event.
IR was earlier to market with actual transistor products -- ahead of Transphorm and Infineon
Power and logic or memory devices have been merged onto single monolithic chips for many years for the lower power and voltage ranges. But the cost-per-unit-area of silicon is one thing that makes this merger of 20 layer and 4 layer devices less economical than simply making the power and CMOS chips separately and then simply putting them in a single package. Power modules were costly in the days when many components had to be packaged together, perhaps with capacitors or inductors and precision thin films. 10,000 volts or 2000 amperes is a different world than 200 volts and 100 amperes. And RF-uWave is a third world.
However with simpler CMOS drivers for Power Mosfets or IGBT's or now HEMT's the two-chip modules are quite cost-effective. And stacked chips are emerging that may include a power layer on heat sink. (Although that is almost as costly as trying to integrate too many technologies on a monolithic chip.)
In my opinion, only in the lower voltage and current levels are monolithic chips cost effective, such as CMOS-DMOS chips. However, someone will find a way to put everyone on one chip for some novel application, or just to prove it can be done. Packaging is where the effort is now, as large wafers have made the power and cmos chips (separately) very cheap.
Both Infineon and IR have been doing that for years just without much overlap in market. Infineon was busy trying to make memory devices for several years, and they did pioneer some great factory systems which can be used for years for "analog" and "power" products even though they are obsolete for memories and higher speed logic. Good marriage perhaps, and both companies have roots in Eastern Europe, with adventures in US and Asia over the years. Remember, the real world is still analog. Digital chips are complex but cheap and best merged with power by two chips in a package. Just my opinion.
MP Divakar: I think Infineon was interested in three things:
1) Digital power technology from Chill arm of IR (probably having some doubts about the Primarion technology they acquired few yrs ago?)
2)GaN technology, as you mentioned
3) Establish a bigger footprint in the US - specifically in CA
1. Integrating Caps / Inductors are better done at the package level where you have a choice of 2D substrate-based packaging as well as 3D stacking. I do not know if it is possible to do Cap / Inductor integration on the same substrate in GaN-on-Si/SiC. I only know of such integrations in Silicon-on-insulators in RF applications.
2. GaN-based power devices typically have higher heat flux in comparison to Si ones. Thermal management therefore needs special attention. Although they have higher operating temperatures, one is limited by the packaging material choices vs. cost. At present, most low cost materials for assembly are good up to 175degC.
3. Regarding your point about compromising in parasitics for lower cost, it depends on the application you are targeting.
@Junko: one more comment I have, stemming from a line in the Yole report you mention above: "...At the risk of being overly-pessimistic, some companies will not survive, and will either be acquired or go bankrupt", says Yole Dévelopement.
I think we are already seeing financing pressures and founder step-downs in some of these startups working on GaN variants, in particular bulk GaN! I think Yole is being more realistic than pessimistic here, the cost of GaN devices even with better figures of merit is just not competitive. As such it will have to be positioned for niche, high breakdown markets.
@Junko: it is interesting that Infineon went after IR even though there are many overlapping products. If technology weighed more than products, it could have gone after companies like Efficient Power Conversion (epc-co.com), another Lidow-connected company that is shipping GaN-on-Si power devices!
Do you think that it is possible to incorperate (-cap and inductors)
GAn on Si with Cmos all on one Ic or is this not an option with todays technology?
Does the GAN have to be at the substrate layer or can it go on top next to the heat sink (think CPU type form factor)
noise issues are partly a function of relative distances because of non ideal layout compromises and parasitics. Thes become less an issue as thes parasitics shrink.
But this is countered by the smaller noise being in closer proximity to sensitive nodes.
As our loads use lower and lower voltages, dynamic or not this can add relief and cost savings.
Heat concentration being a major limiting factor as si can't take the temps of GAN and SiC, unless a temperature diff can be maintained across the barrier between them this could be limiting problem if one wishes to use the GAN at it full temp capacity.
But maybe not if that is not needed to from economics when backed out to the options comparing it to.