So far, Penn State has used three-inch InP substrates on which it deposits InGaAs transistor channels using molecular-beam epitaxy performed at a nearby IQE Inc. facility. On top of the channels, it deposits the five 3D gate fins in what it calls a Multi-fin Hall Bar Structure (MHBS), so named because the researchers claim it is the first structure to allow the measurement of Hall mobility in a multi-fin 3D device. Thathachary used the MHBS to measure any mobility degradation suffered when going from planar transistors to those with 30nm fins. The researchers found that III-V materials would have a 2-3 times the mobility advantage over silicon under specific conditions.
"InGaAs (intrinsic) is the channel which sits on an undoped InAlAs [indium aluminum arsenide] buffer layer," Thathachary said. "The structures, however, have heavily doped InGaAs as the final layer, as well, to facilitate low contact resistance source/drain regions."
Using IsP substrates mostly solves the lattice mismatch problem that plagues trying to grow III-V compounds on silicon substates. But the researchers' charter is only to investigate whether III-V FinFETs will work better than silicon at nodes as advanced as 5 nm. To that end, they are experimenting with various formulations.
"Since these structures are grown on InP/InAlAs layers, the channel is lattice matched in the case of the 53% indium composition InGaAs structures," Thathachary said. "We do have a strained 70% indium channel FinFET, as well, where we designed the channel to be thin to prevent it from relaxing."
Thathachary and Datta have spent a year optimizing the processes for the current 3D FinFET, and the success has prompted Samsung to give the lab another year's funding to prove that it can go to 7nm fins and retain a significant advantage over silicon FinFETs. The researchers have already found several ways to boost mobility, such as using quantum confinement to force electrons to travel inside the channel, rather than along the surface, which degrades mobility because of the roughness there.
If the researchers can demonstrate a 7nm III-V device that can still beat silicon, Samsung will likely internalize further research to integrate III-V FinFETs n-channels with germanium p-channels on silicon substrates for mass production, probably at the 5nm node.
— R. Colin Johnson, Advanced Technology Editor, EE Times